diff options
| -rw-r--r-- | gcc/ChangeLog | 23 | ||||
| -rw-r--r-- | gcc/config/m32c/addsub.md | 6 | ||||
| -rw-r--r-- | gcc/config/m32c/bitops.md | 15 | ||||
| -rw-r--r-- | gcc/config/m32c/cond.md | 25 | ||||
| -rw-r--r-- | gcc/config/m32c/jump.md | 5 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c.c | 251 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c.md | 8 | ||||
| -rw-r--r-- | gcc/config/m32c/minmax.md | 4 | ||||
| -rw-r--r-- | gcc/config/m32c/mov.md | 23 | ||||
| -rw-r--r-- | gcc/config/m32c/muldiv.md | 12 | ||||
| -rw-r--r-- | gcc/config/m32c/prologue.md | 16 | ||||
| -rw-r--r-- | gcc/config/m32c/shift.md | 13 |
13 files changed, 367 insertions, 35 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8a9bdf0..d11b14c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2006-03-31 DJ Delorie <dj@redhat.com> + + * config/m32c/cond.md: Set condition flags properly throughout. + * config/m32c/minmax.md: Likewise. + * config/m32c/prologue.md: Likewise. + * config/m32c/bitops.md: Likewise. + * config/m32c/muldiv.md: Likewise. + * config/m32c/mov.md: Likewise. + * config/m32c/addsub.md: Likewise. + * config/m32c/m32c.md: Likewise. + * config/m32c/jump.md: Likewise. + * config/m32c/shift.md: Likewise. + + * config/m32c/cond.md (cmp<mode>): Call m32c_output_compare to + conditionally output the pattern for this. + * config/m32c/m32c.c (flags_needed_for_conditional): New. + (m32c_compare_redundant): New. + (m32c_output_compare): New. + * config/m32c/m32c-protos.h (m32c_output_compare): New. + + * config/m32c/m32c.c (m32c_prepare_shift): Fix logic to clobber + dest, not src. Allow other 4-byte modes. + 2006-03-30 Denis Chertykov <denisc@overta.ru> * doc/md.texi: Refer to avr/constraints.md instead of diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md index 6ac31dd..8358756 100644 --- a/gcc/config/m32c/addsub.md +++ b/gcc/config/m32c/addsub.md @@ -53,7 +53,7 @@ stc\t%1,%0 mova\t%D2[%1],%0 add.w\t%2,%0" - [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc")] + [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")] ) (define_insn "addpsi3" @@ -69,7 +69,7 @@ add.l\t%2,%0 mova\t%d2[%1],%0 mova\t%D2[%1],%0" - [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,*,*")] + [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")] ) (define_insn "subqi3" @@ -134,7 +134,7 @@ (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))] "" "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0" - [(set_attr "flags" "oszc,oszc")] + [(set_attr "flags" "x")] ) (define_insn "absqi2" diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md index e7823b9..56d6a75 100644 --- a/gcc/config/m32c/bitops.md +++ b/gcc/config/m32c/bitops.md @@ -47,7 +47,7 @@ (match_operand:QI 2 "" "0")))] "TARGET_A16" "bset\t%0[%1]" - [(set_attr "flags" "sz")] + [(set_attr "flags" "n")] ) (define_insn "bset_hi" @@ -57,7 +57,7 @@ (const_int 1))] "TARGET_A16" "bset\t%0[%1]" - [(set_attr "flags" "sz")] + [(set_attr "flags" "n")] ) ;;---------------------------------------------------------------------- @@ -73,7 +73,7 @@ (const_int 0))] "TARGET_A16" "bclr\t%0[%1]" - [(set_attr "flags" "sz")] + [(set_attr "flags" "n")] ) @@ -183,18 +183,17 @@ (define_insn "iorqi3_24" - [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RqiSd,??Rmm,RqiSd,??Rmm") - (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0") - (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))] + [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm") + (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0") + (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))] "TARGET_A24" "@ bset\t%B2,%0 - bset\t%B2,%0 or.b\t%x2,%0 or.b\t%x2,%0 or.b\t%x2,%0 or.b\t%x2,%0" - [(set_attr "flags" "n,n,sz,sz,sz,sz")] + [(set_attr "flags" "n,sz,sz,sz,sz")] ) (define_insn "iorhi3_24" diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md index ad8a5d6..9df4d04 100644 --- a/gcc/config/m32c/cond.md +++ b/gcc/config/m32c/cond.md @@ -60,7 +60,9 @@ "@ stzx\t%1,%2,%0 stz\t%1,%0 - stnz\t%2,%0") + stnz\t%2,%0" + [(set_attr "flags" "n,n,n")] +) (define_insn "stzx_24_<mode>" [(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd") @@ -71,7 +73,8 @@ "@ stzx.<bwl>\t%1,%2,%0 stz.<bwl>\t%1,%0 - stnz.<bwl>\t%2,%0") + stnz.<bwl>\t%2,%0" + [(set_attr "flags" "n,n,n")]) (define_insn_and_split "stzx_reversed" [(set (match_operand 0 "m32c_r0_operand" "") @@ -94,7 +97,8 @@ (compare (match_operand:QHPSI 0 "mra_operand" "RraSd") (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))] "" - "cmp.<bwl>\t%1,%0") + "* return m32c_output_compare(insn, operands); " + [(set_attr "flags" "oszc")]) (define_insn "b<code>" [(set (pc) @@ -104,6 +108,7 @@ (pc)))] "" "j<code>\t%l0" + [(set_attr "flags" "n")] ) ;; m32c_conditional_register_usage changes the setcc_gen_code array to @@ -119,7 +124,9 @@ [(set (match_operand:HI 0 "mra_operand" "=RhiSd") (any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))] "TARGET_A24" - "sc<code>\t%0") + "sc<code>\t%0" + [(set_attr "flags" "n")] +) (define_expand "movqicc" [(set (match_operand:QI 0 "register_operand" "") @@ -148,10 +155,10 @@ ;; value. This pattern recovers the sign of the discarded value based ;; on the flags. Operand 0 is set to -1, 0, or 1. This is used for ;; the cmpstr pattern. For optimal code, this should be removed if -;; followed by a suitable CMP insn, as SCMPU sets the flags correctly -;; already (see the peephole following). This pattern is 7 bytes and -;; 5 cycles. If you don't need specific values, a 5/4 pattern can be -;; made with SCGT and BMLT to set the appropriate bits. +;; followed by a suitable CMP insn (see the peephole following). This +;; pattern is 7 bytes and 5 cycles. If you don't need specific +;; values, a 5/4 pattern can be made with SCGT and BMLT to set the +;; appropriate bits. (define_insn "cond_to_int" [(set (match_operand:HI 0 "mra_qi_operand" "=Rqi") @@ -162,7 +169,7 @@ (const_int -1))))] "TARGET_A24" "sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0" - [(set_attr "flags" "sz")] + [(set_attr "flags" "x")] ) ;; A cond_to_int followed by a compare against zero is essentially a no-op. diff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md index 705bb32..5507fb4 100644 --- a/gcc/config/m32c/jump.md +++ b/gcc/config/m32c/jump.md @@ -29,6 +29,7 @@ ; "jmpi.a\t%0" ; no 16 bit jmpi in r8c "push.b #0 | push.w\t%0 | rts" + [(set_attr "flags" "x")] ) (define_insn "indirect_jump_24" @@ -36,6 +37,7 @@ (match_operand:PSI 0 "register_operand" "Rpi"))] "TARGET_A24" "jmpi.a\t%0" + [(set_attr "flags" "n")] ) (define_expand "indirect_jump" @@ -56,6 +58,7 @@ (label_ref (match_operand 0 "" "")))] "" "jmp.a\t%l0" + [(set_attr "flags" "n")] ) ; No 16 bit indirect calls on r8c/m16c. */ @@ -70,6 +73,7 @@ switch (which_alternative) { case 1: return TARGET_A16 ? \"push.w %a0 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a0\"; case 2: return \"jsri.a\t%a0\"; }" + [(set_attr "flags" "x")] ) (define_insn "call_value" @@ -84,4 +88,5 @@ switch (which_alternative) { case 1: return TARGET_A16 ? \"push.w %a1 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a1\"; case 2: return \"jsri.a\t%a1\"; }" + [(set_attr "flags" "x,x,x")] ) diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h index eb97796..a7bcd33 100644 --- a/gcc/config/m32c/m32c-protos.h +++ b/gcc/config/m32c/m32c-protos.h @@ -84,6 +84,7 @@ int m32c_memory_move_cost (MM, int, int); int m32c_mode_dependent_address (rtx); int m32c_modes_tieable_p (MM, MM); bool m32c_mov_ok (rtx *, MM); +char * m32c_output_compare (rtx, rtx *); int m32c_preferred_output_reload_class (rtx, int); int m32c_preferred_reload_class (rtx, int); int m32c_prepare_move (rtx *, MM); diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 0f7269b..3625640 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -3291,9 +3291,8 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code) else /* We'll only use it for the shift, no point emitting a move. */ temp = operands[2]; - - if (TARGET_A16 && mode == SImode) + if (TARGET_A16 && GET_MODE_SIZE (mode) == 4) { /* The m16c has a limit of -16..16 for SI shifts, even when the shift count is in a register. Since there are so many targets @@ -3318,6 +3317,8 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code) rtx count; rtx label, lref, insn; + emit_move_insn (operands[0], operands[1]); + count = temp; label = gen_label_rtx (); lref = gen_rtx_LABEL_REF (VOIDmode, label); @@ -3328,8 +3329,8 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code) /* This is a left shift. We only need check positive counts. */ emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0), count, GEN_INT (16), label)); - emit_insn (func (operands[1], operands[1], GEN_INT (8))); - emit_insn (func (operands[1], operands[1], GEN_INT (8))); + emit_insn (func (operands[0], operands[0], GEN_INT (8))); + emit_insn (func (operands[0], operands[0], GEN_INT (8))); insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16))); emit_label_after (label, insn); } @@ -3338,12 +3339,14 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code) /* This is a right shift. We only need check negative counts. */ emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0), count, GEN_INT (-16), label)); - emit_insn (func (operands[1], operands[1], GEN_INT (-8))); - emit_insn (func (operands[1], operands[1], GEN_INT (-8))); + emit_insn (func (operands[0], operands[0], GEN_INT (-8))); + emit_insn (func (operands[0], operands[0], GEN_INT (-8))); insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16))); emit_label_after (label, insn); } - + operands[1] = operands[0]; + emit_insn (func (operands[0], operands[0], count)); + return 1; } operands[2] = temp; @@ -3459,6 +3462,7 @@ m32c_expand_insv (rtx *operands) storing a zero, we want an AND mask, so invert it. */ if (INTVAL (operands[3]) == 0) { + /* Storing a zero, use an AND mask */ if (GET_MODE (op0) == HImode) mask ^= 0xffff; else @@ -3691,6 +3695,239 @@ m32c_emit_eh_epilogue (rtx ret_addr) emit_barrier (); } +/* Indicate which flags must be properly set for a given conditional. */ +static int +flags_needed_for_conditional (rtx cond) +{ + switch (GET_CODE (cond)) + { + case LE: + case GT: + return FLAGS_OSZ; + case LEU: + case GTU: + return FLAGS_ZC; + case LT: + case GE: + return FLAGS_OS; + case LTU: + case GEU: + return FLAGS_C; + case EQ: + case NE: + return FLAGS_Z; + default: + return FLAGS_N; + } +} + +#define DEBUG_CMP 0 + +/* Returns true if a compare insn is redundant because it would only + set flags that are already set correctly. */ +static bool +m32c_compare_redundant (rtx cmp, rtx *operands) +{ + int flags_needed; + int pflags; + rtx prev, pp, next; + rtx op0, op1, op2; +#if DEBUG_CMP + int prev_icode, i; +#endif + + op0 = operands[0]; + op1 = operands[1]; + op2 = operands[2]; + +#if DEBUG_CMP + fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n"); + debug_rtx(cmp); + for (i=0; i<2; i++) + { + fprintf(stderr, "operands[%d] = ", i); + debug_rtx(operands[i]); + } +#endif + + next = next_nonnote_insn (cmp); + if (!next || !INSN_P (next)) + { +#if DEBUG_CMP + fprintf(stderr, "compare not followed by insn\n"); + debug_rtx(next); +#endif + return false; + } + if (GET_CODE (PATTERN (next)) == SET + && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE) + { + next = XEXP (XEXP (PATTERN (next), 1), 0); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + /* If this is a conditional, flags_needed will be something + other than FLAGS_N, which we test below. */ + next = XEXP (PATTERN (next), 1); + } + else + { +#if DEBUG_CMP + fprintf(stderr, "compare not followed by conditional\n"); + debug_rtx(next); +#endif + return false; + } +#if DEBUG_CMP + fprintf(stderr, "conditional is: "); + debug_rtx(next); +#endif + + flags_needed = flags_needed_for_conditional (next); + if (flags_needed == FLAGS_N) + { +#if DEBUG_CMP + fprintf(stderr, "compare not followed by conditional\n"); + debug_rtx(next); +#endif + return false; + } + + /* Compare doesn't set overflow and carry the same way that + arithmetic instructions do, so we can't replace those. */ + if (flags_needed & FLAGS_OC) + return false; + + prev = cmp; + do { + prev = prev_nonnote_insn (prev); + if (!prev) + { +#if DEBUG_CMP + fprintf(stderr, "No previous insn.\n"); +#endif + return false; + } + if (!INSN_P (prev)) + { +#if DEBUG_CMP + fprintf(stderr, "Previous insn is a non-insn.\n"); +#endif + return false; + } + pp = PATTERN (prev); + if (GET_CODE (pp) != SET) + { +#if DEBUG_CMP + fprintf(stderr, "Previous insn is not a SET.\n"); +#endif + return false; + } + pflags = get_attr_flags (prev); + + /* Looking up attributes of previous insns corrupted the recog + tables. */ + INSN_UID (cmp) = -1; + recog (PATTERN (cmp), cmp, 0); + + if (pflags == FLAGS_N + && reg_mentioned_p (op0, pp)) + { +#if DEBUG_CMP + fprintf(stderr, "intermediate non-flags insn uses op:\n"); + debug_rtx(prev); +#endif + return false; + } + } while (pflags == FLAGS_N); +#if DEBUG_CMP + fprintf(stderr, "previous flag-setting insn:\n"); + debug_rtx(prev); + debug_rtx(pp); +#endif + + if (GET_CODE (pp) == SET + && GET_CODE (XEXP (pp, 0)) == REG + && REGNO (XEXP (pp, 0)) == FLG_REGNO + && GET_CODE (XEXP (pp, 1)) == COMPARE) + { + /* Adjacent cbranches must have the same operands to be + redundant. */ + rtx pop0 = XEXP (XEXP (pp, 1), 0); + rtx pop1 = XEXP (XEXP (pp, 1), 1); +#if DEBUG_CMP + fprintf(stderr, "adjacent cbranches\n"); + debug_rtx(pop0); + debug_rtx(pop1); +#endif + if (rtx_equal_p (op0, pop0) + && rtx_equal_p (op1, pop1)) + return true; +#if DEBUG_CMP + fprintf(stderr, "prev cmp not same\n"); +#endif + return false; + } + + /* Else the previous insn must be a SET, with either the source or + dest equal to operands[0], and operands[1] must be zero. */ + + if (!rtx_equal_p (op1, const0_rtx)) + { +#if DEBUG_CMP + fprintf(stderr, "operands[1] not const0_rtx\n"); +#endif + return false; + } + if (GET_CODE (pp) != SET) + { +#if DEBUG_CMP + fprintf (stderr, "pp not set\n"); +#endif + return false; + } + if (!rtx_equal_p (op0, SET_SRC (pp)) + && !rtx_equal_p (op0, SET_DEST (pp))) + { +#if DEBUG_CMP + fprintf(stderr, "operands[0] not found in set\n"); +#endif + return false; + } + +#if DEBUG_CMP + fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags); +#endif + if ((pflags & flags_needed) == flags_needed) + return true; + + return false; +} + +/* Return the pattern for a compare. This will be commented out if + the compare is redundant, else a normal pattern is returned. Thus, + the assembler output says where the compare would have been. */ +char * +m32c_output_compare (rtx insn, rtx *operands) +{ + static char template[] = ";cmp.b\t%1,%0"; + /* ^ 5 */ + + template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))]; + if (m32c_compare_redundant (insn, operands)) + { +#if DEBUG_CMP + fprintf(stderr, "cbranch: cmp not needed\n"); +#endif + return template; + } + +#if DEBUG_CMP + fprintf(stderr, "cbranch: cmp needed: `%s'\n", template); +#endif + return template + 1; +} + /* The Global `targetm' Variable. */ struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md index f1930d4..cffa5ba 100644 --- a/gcc/config/m32c/m32c.md +++ b/gcc/config/m32c/m32c.md @@ -70,9 +70,13 @@ (define_insn "nop" [(const_int 0)] "" - "nop") + "nop" + [(set_attr "flags" "n")] +) (define_insn "no_insn" [(const_int 1)] "" - "") + "" + [(set_attr "flags" "n")] +) diff --git a/gcc/config/m32c/minmax.md b/gcc/config/m32c/minmax.md index de0ea4f..21d63dc 100644 --- a/gcc/config/m32c/minmax.md +++ b/gcc/config/m32c/minmax.md @@ -28,6 +28,7 @@ (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))] "TARGET_A24" "min.b\t%2,%0" + [(set_attr "flags" "n")] ) (define_insn "sminhi3" @@ -36,6 +37,7 @@ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))] "TARGET_A24" "min.w\t%2,%0" + [(set_attr "flags" "n")] ) (define_insn "smaxqi3" @@ -44,6 +46,7 @@ (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))] "TARGET_A24" "max.b\t%2,%0" + [(set_attr "flags" "n")] ) (define_insn "smaxhi3" @@ -52,4 +55,5 @@ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))] "TARGET_A24" "max.w\t%2,%0" + [(set_attr "flags" "n")] ) diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md index 1a6878d..791ac5d 100644 --- a/gcc/config/m32c/mov.md +++ b/gcc/config/m32c/mov.md @@ -71,7 +71,7 @@ pop.w\t%0 pushc\t%1 popc\t%0" - [(set_attr "flags" "sz,sz,sz,*,*,*,*,*,*")] + [(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")] ) (define_expand "movhi" @@ -97,7 +97,7 @@ pushc\t%1 popc\t%0 #" - [(set_attr "flags" "sz,sz,*,*,*,*,*,*")] + [(set_attr "flags" "sz,sz,n,n,n,n,n,*")] ) @@ -182,6 +182,7 @@ (match_operand 0 "a_operand" "Raa"))] "" "push.l\t%0" + [(set_attr "flags" "n")] ) (define_insn "movsi_24" @@ -193,6 +194,7 @@ mov.l\t%1,%0 # push.l\t%1" + [(set_attr "flags" "sz,sz,*,n")] ) (define_expand "movdi" @@ -220,6 +222,7 @@ (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))] "" "push.b\t%0" + [(set_attr "flags" "n")] ) (define_expand "pushhi" @@ -240,6 +243,7 @@ "@ push.w\t%0 pushc\t%0" + [(set_attr "flags" "n,n")] ) (define_insn "pushhi_24" @@ -247,6 +251,7 @@ (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))] "TARGET_A24" "push.w\t%0" + [(set_attr "flags" "n")] ) ;(define_insn "pushpi" @@ -263,6 +268,7 @@ (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))] "TARGET_A24" "push.l\t%0" + [(set_attr "flags" "n")] ) (define_expand "pophi" @@ -283,6 +289,7 @@ "@ pop.w\t%0 popc\t%0" + [(set_attr "flags" "n,n")] ) (define_insn "pophi_24" @@ -290,6 +297,7 @@ (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))] "TARGET_A24" "pop.w\t%0" + [(set_attr "flags" "n")] ) (define_insn "poppsi" @@ -297,6 +305,7 @@ (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))] "TARGET_A24" "popc\t%0" + [(set_attr "flags" "n")] ) @@ -316,7 +325,7 @@ "* if (REGNO(operands[0]) == 0) return \"exts.w\t%1\"; else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";" - [(set_attr "flags" "sz")] + [(set_attr "flags" "x")] ) (define_insn "extendpsisi2" @@ -324,6 +333,7 @@ (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))] "" "; expand psi %1 to si %0" + [(set_attr "flags" "n")] ) (define_insn "zero_extendpsisi2" @@ -331,6 +341,7 @@ (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))] "" "; expand psi %1 to si %0" + [(set_attr "flags" "n")] ) (define_insn "zero_extendhipsi2" @@ -338,6 +349,7 @@ (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))] "" "mov.w\t%1,%0" + [(set_attr "flags" "sz")] ) (define_insn "zero_extendhisi2" @@ -345,6 +357,7 @@ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))] "" "mov.w\t#0,%H0" + [(set_attr "flags" "x")] ) (define_insn "zero_extendqihi2" @@ -354,6 +367,7 @@ "@ mov.b\t#0,%H0 and.w\t#255,%0" + [(set_attr "flags" "x,x")] ) (define_insn "truncsipsi2_16" @@ -365,6 +379,7 @@ # ldc\t%1,%0 stc\t%1,%0" + [(set_attr "flags" "n,*,n,n")] ) (define_insn "trunchiqi2" @@ -372,6 +387,7 @@ (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))] "" "; no-op trunc hi %1 to qi %0" + [(set_attr "flags" "n")] ) (define_insn "truncsipsi2_24" @@ -383,6 +399,7 @@ mov.l\t%1,%0 ldc\t%1,%0 stc\t%1,%0" + [(set_attr "flags" "n,sz,n,n")] ) (define_expand "truncsipsi2" diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md index 038ca8a..a4bde64 100644 --- a/gcc/config/m32c/muldiv.md +++ b/gcc/config/m32c/muldiv.md @@ -29,6 +29,7 @@ (match_operand 2 "immediate_operand" "i,i")))] "" "mul.b\t%2,%1" + [(set_attr "flags" "o")] ) ; Here is the pattern for registers and such. @@ -38,6 +39,7 @@ (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))] "" "mul.b\t%2,%1" + [(set_attr "flags" "o")] ) ; Don't try to sign_extend a const_int. Same for all other multiplies. @@ -56,6 +58,7 @@ (match_operand 2 "immediate_operand" "i,i")))] "" "mulu.b\t%U2,%1" + [(set_attr "flags" "o")] ) (define_insn "umulqihi3_r" @@ -64,6 +67,7 @@ (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))] "" "mulu.b\t%U2,%1" + [(set_attr "flags" "o")] ) (define_expand "umulqihi3" @@ -81,6 +85,7 @@ (match_operand 2 "immediate_operand" "i,i")))] "" "mul.w\t%2,%1" + [(set_attr "flags" "o")] ) (define_insn "mulhisi3_r" @@ -89,6 +94,7 @@ (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))] "" "mul.w\t%2,%1" + [(set_attr "flags" "o")] ) (define_expand "mulhisi3" @@ -106,6 +112,7 @@ (match_operand 2 "immediate_operand" "i,i")))] "" "mulu.w\t%u2,%1" + [(set_attr "flags" "o")] ) (define_insn "umulhisi3_r" @@ -114,6 +121,7 @@ (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))] "" "mulu.w\t%u2,%1" + [(set_attr "flags" "o")] ) (define_expand "umulhisi3" @@ -175,6 +183,7 @@ ] "0" "div.b\t%2" + [(set_attr "flags" "o")] ) (define_expand "udivmodqi4" @@ -199,6 +208,7 @@ ] "0" "divu.b\t%2" + [(set_attr "flags" "o")] ) (define_expand "divmodhi4" @@ -223,6 +233,7 @@ ] "" "div.w\t%2" + [(set_attr "flags" "o")] ) (define_expand "udivmodhi4" @@ -247,4 +258,5 @@ ] "" "divu.w\t%2" + [(set_attr "flags" "o")] ) diff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md index 7e78594..98c40ac 100644 --- a/gcc/config/m32c/prologue.md +++ b/gcc/config/m32c/prologue.md @@ -43,6 +43,7 @@ ] "TARGET_A16" "enter\t%0" + [(set_attr "flags" "x")] ) (define_insn "prologue_enter_24" @@ -56,6 +57,7 @@ ] "TARGET_A24" "enter\t%0" + [(set_attr "flags" "x")] ) ; Just a comment, for debugging the assembler output. @@ -63,6 +65,7 @@ [(unspec_volatile [(const_int 0)] UNS_PROLOGUE_END)] "" "; end of prologue" + [(set_attr "flags" "n")] ) @@ -86,6 +89,7 @@ ] UNS_EH_EPILOGUE))] "" "jmp.a\t__m32c_eh_return" + [(set_attr "flags" "x")] ) (define_insn "epilogue_exitd" @@ -100,6 +104,7 @@ ] "" "exitd" + [(set_attr "flags" "x")] ) (define_insn "epilogue_reit" @@ -110,6 +115,7 @@ ] "" "reit" + [(set_attr "flags" "x")] ) (define_insn "epilogue_rts" @@ -117,12 +123,14 @@ ] "" "rts" + [(set_attr "flags" "x")] ) (define_insn "epilogue_start" [(unspec_volatile [(const_int 0)] UNS_EPILOGUE_START)] "" "; start of epilogue" + [(set_attr "flags" "n")] ) @@ -131,9 +139,13 @@ (define_insn "pushm" [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_PUSHM)] "" - "pushm\t%p0") + "pushm\t%p0" + [(set_attr "flags" "n")] + ) (define_insn "popm" [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_POPM)] "" - "popm\t%p0") + "popm\t%p0" + [(set_attr "flags" "n")] + ) diff --git a/gcc/config/m32c/shift.md b/gcc/config/m32c/shift.md index 3e07b25..6679f38 100644 --- a/gcc/config/m32c/shift.md +++ b/gcc/config/m32c/shift.md @@ -39,6 +39,7 @@ "@ sha.b\t%2,%0 mov.b\t%2,r1h\n\tsha.b\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "ashrqi3_i" @@ -50,6 +51,7 @@ "@ sha.b\t%2,%0 mov.b\t%2,r1h\n\tsha.b\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "lshrqi3_i" @@ -61,6 +63,7 @@ "@ shl.b\t%2,%0 mov.b\t%2,r1h\n\tshl.b\tr1h,%0" + [(set_attr "flags" "szc,szc")] ) @@ -105,6 +108,7 @@ "@ sha.w\t%2,%0 mov.b\t%2,r1h\n\tsha.w\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "ashrhi3_i" @@ -116,6 +120,7 @@ "@ sha.w\t%2,%0 mov.b\t%2,r1h\n\tsha.w\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "lshrhi3_i" @@ -127,6 +132,7 @@ "@ shl.w\t%2,%0 mov.b\t%2,r1h\n\tshl.w\tr1h,%0" + [(set_attr "flags" "szc,szc")] ) @@ -175,6 +181,7 @@ "@ sha.l\t%2,%0 mov.b\t%2,r1h\n\tsha.l\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "ashrpsi3_i" @@ -186,6 +193,7 @@ "@ sha.l\t%2,%0 mov.b\t%2,r1h\n\tsha.l\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "lshrpsi3_i" @@ -197,6 +205,7 @@ "@ shl.l\t%2,%0 mov.b\t%2,r1h\n\tshl.l\tr1h,%0" + [(set_attr "flags" "szc,szc")] ) @@ -248,7 +257,7 @@ "@ sha.l\t%2,%0 mov.b\t%2,r1h\n\tsha.l\tr1h,%0" - [(set_attr "flags" "sz,sz")] + [(set_attr "flags" "oszc,oszc")] ) (define_insn "ashrsi3_16" @@ -260,6 +269,7 @@ "@ sha.l\t%2,%0 mov.b\t%2,r1h\n\tsha.l\tr1h,%0" + [(set_attr "flags" "oszc,oszc")] ) (define_insn "lshrsi3_16" @@ -271,6 +281,7 @@ "@ shl.l\t%2,%0 mov.b\t%2,r1h\n\tshl.l\tr1h,%0" + [(set_attr "flags" "szc,szc")] ) |