diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 15 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 |
3 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3782894..f967111 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-08-01 Jiong Wang <jiong.wang@arm.com> + + * config/aarch64/aarch64.c (aarch64_classify_address): Accept all offset + for frame access when strict_p is false. + 2014-08-01 Renlin Li <renlin.li@arm.com> 2014-08-01 Jiong Wang <jiong.wang@arm.com> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d3f2adb..7e135a1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3248,6 +3248,21 @@ aarch64_classify_address (struct aarch64_address_info *info, case PLUS: op0 = XEXP (x, 0); op1 = XEXP (x, 1); + + if (! strict_p + && GET_CODE (op0) == REG + && (op0 == virtual_stack_vars_rtx + || op0 == frame_pointer_rtx + || op0 == arg_pointer_rtx) + && GET_CODE (op1) == CONST_INT) + { + info->type = ADDRESS_REG_IMM; + info->base = op0; + info->offset = op1; + + return true; + } + if (GET_MODE_SIZE (mode) != 0 && CONST_INT_P (op1) && aarch64_base_register_rtx_p (op0, strict_p)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e29098f..cc4e3d1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-08-01 Jiong Wang <jiong.wang@arm.com> + + * gcc.target/aarch64/legitimize_stack_var_before_reload_1.c: New + testcase. + 2014-08-01 Richard Biener <rguenther@suse.de> PR middle-end/61762 |