diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/c-family/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/c-family/c-opts.cc | 32 | ||||
| -rw-r--r-- | gcc/config/i386/i386.cc | 82 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 43 | ||||
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 1 | ||||
| -rw-r--r-- | gcc/config/riscv/vector.md | 13 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/g++.dg/cpp0x/constexpr-temp3.C | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c | 2 |
15 files changed, 146 insertions, 60 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index afa194e..2814c52 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2025-05-03 Jan Hubicka <hubicka@ucw.cz> + + * config/i386/i386.cc (unspec_pcmp_p): New function. + (ix86_rtx_costs): Cost VEC_MERGE more realistically. + 2025-05-02 Andrew Pinski <quic_apinski@quicinc.com> PR rtl-optimization/120059 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 2d83869..e49f233 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250503 +20250504 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 1572c8b..9ff3338 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,8 @@ +2025-05-03 Jason Merrill <jason@redhat.com> + + * c-opts.cc (c_common_post_options): Let plain -Wabi warn + about changes in a future version. + 2025-04-28 David Malcolm <dmalcolm@redhat.com> * c-pretty-print.cc: Drop include of "make-unique.h". diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc index 4016382..f1c276f 100644 --- a/gcc/c-family/c-opts.cc +++ b/gcc/c-family/c-opts.cc @@ -1085,12 +1085,21 @@ c_common_post_options (const char **pfilename) /* Change flag_abi_version to be the actual current ABI level, for the benefit of c_cpp_builtins, and to make comparison simpler. */ const int latest_abi_version = 21; + /* Possibly different for non-default ABI fixes within a release. */ + const int default_abi_version = latest_abi_version; /* Generate compatibility aliases for ABI v18 (GCC 13) by default. */ const int abi_compat_default = 18; + if (flag_abi_version > latest_abi_version) + warning (0, "%<-fabi-version=%d%> is not supported, using =%d", + flag_abi_version, latest_abi_version); + + SET_OPTION_IF_UNSET (&global_options, &global_options_set, + flag_abi_version, default_abi_version); + #define clamp(X) if (X == 0 || X > latest_abi_version) X = latest_abi_version clamp (flag_abi_version); - clamp (warn_abi_version); + /* Don't clamp warn_abi_version, let it be 0 or out of bounds. */ clamp (flag_abi_compat_version); #undef clamp @@ -1101,24 +1110,17 @@ c_common_post_options (const char **pfilename) flag_abi_compat_version = warn_abi_version; else if (warn_abi_version == -1 && flag_abi_compat_version == -1) { - warn_abi_version = latest_abi_version; - if (flag_abi_version == latest_abi_version) - { - auto_diagnostic_group d; - if (warning (OPT_Wabi, "%<-Wabi%> won%'t warn about anything")) - { - inform (input_location, "%<-Wabi%> warns about differences " - "from the most up-to-date ABI, which is also used " - "by default"); - inform (input_location, "use e.g. %<-Wabi=11%> to warn about " - "changes from GCC 7"); - } - flag_abi_compat_version = abi_compat_default; - } + warn_abi_version = 0; + if (flag_abi_version == default_abi_version) + flag_abi_compat_version = abi_compat_default; else flag_abi_compat_version = latest_abi_version; } + /* Allow warnings vs ABI versions beyond what we currently support. */ + if (warn_abi_version == 0) + warn_abi_version = 1000; + /* By default, enable the new inheriting constructor semantics along with ABI 11. New and old should coexist fine, but it is a change in what artificial symbols are generated. */ diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 0c808c2..5ad47e1 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -22025,6 +22025,15 @@ vec_fp_conversion_cost (const struct processor_costs *cost, int size) return cost->vcvtps2pd512; } +/* Return true of X is UNSPEC with UNSPEC_PCMP or UNSPEC_UNSIGNED_PCMP. */ + +static bool +unspec_pcmp_p (rtx x) +{ + return GET_CODE (x) == UNSPEC + && (XINT (x, 1) == UNSPEC_PCMP || XINT (x, 1) == UNSPEC_UNSIGNED_PCMP); +} + /* Compute a (partial) cost for rtx X. Return true if the complete cost has been computed, and false if subexpressions should be scanned. In either case, *TOTAL contains the cost result. */ @@ -22807,14 +22816,77 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, case VEC_MERGE: mask = XEXP (x, 2); + /* Scalar versions of SSE instructions may be represented as: + + (vec_merge (vec_duplicate (operation ....)) + (register or memory) + (const_int 1)) + + In this case vec_merge and vec_duplicate is for free. + Just recurse into operation and second operand. */ + if (mask == const1_rtx + && GET_CODE (XEXP (x, 0)) == VEC_DUPLICATE) + { + *total = rtx_cost (XEXP (XEXP (x, 0), 0), mode, + outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed); + return true; + } /* This is masked instruction, assume the same cost, as nonmasked variant. */ - if (TARGET_AVX512F && register_operand (mask, GET_MODE (mask))) - *total = rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed); + else if (TARGET_AVX512F && register_operand (mask, GET_MODE (mask))) + { + *total = rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed); + return true; + } + /* Combination of the two above: + + (vec_merge (vec_merge (vec_duplicate (operation ...)) + (register or memory) + (reg:QI mask)) + (register or memory) + (const_int 1)) + + i.e. avx512fp16_vcvtss2sh_mask. */ + else if (TARGET_AVX512F + && mask == const1_rtx + && GET_CODE (XEXP (x, 0)) == VEC_MERGE + && GET_CODE (XEXP (XEXP (x, 0), 0)) == VEC_DUPLICATE + && register_operand (XEXP (XEXP (x, 0), 2), + GET_MODE (XEXP (XEXP (x, 0), 2)))) + { + *total = rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0), + mode, outer_code, opno, speed) + + rtx_cost (XEXP (XEXP (x, 0), 1), + mode, outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed); + return true; + } + /* vcmp. */ + else if (unspec_pcmp_p (mask) + || (GET_CODE (mask) == NOT + && unspec_pcmp_p (XEXP (mask, 0)))) + { + rtx uns = GET_CODE (mask) == NOT ? XEXP (mask, 0) : mask; + rtx unsop0 = XVECEXP (uns, 0, 0); + /* Make (subreg:V4SI (not:V16QI (reg:V16QI ..)) 0) + cost the same as register. + This is used by avx_cmp<mode>3_ltint_not. */ + if (GET_CODE (unsop0) == SUBREG) + unsop0 = XEXP (unsop0, 0); + if (GET_CODE (unsop0) == NOT) + unsop0 = XEXP (unsop0, 0); + *total = rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed) + + rtx_cost (unsop0, mode, UNSPEC, opno, speed) + + rtx_cost (XVECEXP (uns, 0, 1), mode, UNSPEC, opno, speed) + + cost->sse_op; + return true; + } else - /* ??? We should still recruse when computing cost. */ *total = cost->sse_op; - return true; + return false; case MEM: /* CONST_VECTOR_DUPLICATE_P in constant_pool is just broadcast. @@ -22831,7 +22903,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, } /* An insn that accesses memory is slightly more expensive - than one that does not. */ + than one that does not. */ if (speed) { *total += 1; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ed635ab..10e0f4a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -12047,27 +12047,30 @@ riscv_emit_frm_mode_set (int mode, int prev_mode) if (prev_mode == riscv_vector::FRM_DYN_CALL) emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */ - if (mode != prev_mode) - { - rtx frm = gen_int_mode (mode, SImode); - - if (mode == riscv_vector::FRM_DYN_CALL - && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun)) - /* No need to emit when prev mode is DYN already. */ - emit_insn (gen_fsrmsi_restore_volatile (backup_reg)); - else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun) - && prev_mode != riscv_vector::FRM_DYN - && prev_mode != riscv_vector::FRM_DYN_CALL) - /* No need to emit when prev mode is DYN or DYN_CALL already. */ - emit_insn (gen_fsrmsi_restore_volatile (backup_reg)); - else if (mode == riscv_vector::FRM_DYN - && prev_mode != riscv_vector::FRM_DYN_CALL) - /* Restore frm value from backup when switch to DYN mode. */ - emit_insn (gen_fsrmsi_restore (backup_reg)); - else if (riscv_static_frm_mode_p (mode)) - /* Set frm value when switch to static mode. */ - emit_insn (gen_fsrmsi_restore (frm)); + if (mode == prev_mode) + return; + + if (riscv_static_frm_mode_p (mode)) + { + /* Set frm value when switch to static mode. */ + emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode))); + return; } + + bool restore_p + = /* No need to emit when prev mode is DYN. */ + (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_CALL + && prev_mode != riscv_vector::FRM_DYN) + /* No need to emit if prev mode is DYN or DYN_CALL. */ + || (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_EXIT + && prev_mode != riscv_vector::FRM_DYN + && prev_mode != riscv_vector::FRM_DYN_CALL) + /* Restore frm value when switch to DYN mode. */ + || (mode == riscv_vector::FRM_DYN + && prev_mode != riscv_vector::FRM_DYN_CALL); + + if (restore_p) + emit_insn (gen_fsrmsi_restore (backup_reg)); } /* Implement Mode switching. */ diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 5687e8a..b4c86909 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -124,7 +124,6 @@ ]) (define_c_enum "unspecv" [ - UNSPECV_FRM_RESTORE_EXIT UNSPECV_SF_CV ]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5191ae4..851ba4a 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1115,19 +1115,6 @@ (set_attr "mode" "SI")] ) -;; The volatile fsrmsi restore is used for the exit point for the -;; dynamic mode switching. It will generate one volatile fsrm a5 -;; which won't be eliminated. -(define_insn "fsrmsi_restore_volatile" - [(set (reg:SI FRM_REGNUM) - (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] - UNSPECV_FRM_RESTORE_EXIT))] - "TARGET_VECTOR" - "fsrm\t%0" - [(set_attr "type" "wrfrm") - (set_attr "mode" "SI")] -) - ;; Read FRM (define_insn "frrmsi" [(set (match_operand:SI 0 "register_operand" "=r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0c034bf..0d4d715 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2025-05-03 Jason Merrill <jason@redhat.com> + + PR c++/85944 + * g++.dg/cpp0x/constexpr-temp3.C: New test. + 2025-05-02 Andrew Pinski <quic_apinski@quicinc.com> PR rtl-optimization/120059 diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-temp3.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-temp3.C new file mode 100644 index 0000000..584472c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-temp3.C @@ -0,0 +1,8 @@ +// PR c++/85944 +// { dg-do compile { target c++11 } } + +constexpr bool f(int const & x) { + return &x; +} + +constexpr auto x = f(0); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c index af89f62..3e8a980 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c index 5b75935..e8fc7bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c index cd23141..9828987 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c index fb57803..c8a5800 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c @@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c index 09067d3..186f6c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c @@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ |