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| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 20 |
2 files changed, 24 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9849127..9bf9bc2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2005-06-29 Richard Henderson <rth@redhat.com> + * config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New. + +2005-06-29 Richard Henderson <rth@redhat.com> + * tree-vect-transform.c (vect_min_worthwhile_factor): Declare. (vect_create_epilog_for_reduction): Don't use vec_shr if the operation is emulated. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 157e8ca..35cc320 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6361,6 +6361,26 @@ "" "eqv %1,%2,%0" [(set_attr "type" "ilog")]) + +(define_expand "vec_shl_<mode>" + [(set (match_operand:VEC 0 "register_operand" "") + (ashift:DI (match_operand:VEC 1 "register_operand" "") + (match_operand:DI 2 "reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) + +(define_expand "vec_shr_<mode>" + [(set (match_operand:VEC 0 "register_operand" "") + (lshiftrt:DI (match_operand:VEC 1 "register_operand" "") + (match_operand:DI 2 "reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) ;; Bit field extract patterns which use ext[wlq][lh] |