diff options
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/mips/mips-msa.md | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 10 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/msa-ds.c | 31 |
5 files changed, 58 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b36834b..3516235 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2019-11-19 Zoran Jovanovic <zoran.jovanovic@mips.com> + Dragan Mladjenovic <dmladjenovic@wavecomp.com> + + * config/mips/mips-msa.md (msa_<msabr>_<msafmt_f>, msa_<msabr>_v_<msafmt_f>): + Mark as not having "likely" version. + * config/mips/mips.md (insn_count): The simd_div instruction with + TARGET_CHECK_ZERO_DIV consists of 3 instructions. + (can_delay): Exclude simd_branch. + (defile_delay *): Add simd_branch instructions. + They have one regular delay slot. + 2019-11-19 Martin Liska <mliska@suse.cz> * toplev.c (general_init): Move the call... diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 628423d..100cf99 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -2719,7 +2719,8 @@ } [(set_attr "type" "simd_branch") (set_attr "mode" "<MODE>") - (set_attr "compact_form" "never")]) + (set_attr "compact_form" "never") + (set_attr "branch_likely" "no")]) (define_insn "msa_<msabr>_v_<msafmt_f>" [(set (pc) (if_then_else @@ -2738,4 +2739,5 @@ } [(set_attr "type" "simd_branch") (set_attr "mode" "TI") - (set_attr "compact_form" "never")]) + (set_attr "compact_form" "never") + (set_attr "branch_likely" "no")]) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4de9731..929e368 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -560,6 +560,12 @@ (eq_attr "type" "idiv,idiv3") (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))") + ;; simd div have 3 instruction if TARGET_CHECK_ZERO_DIV is true. + (eq_attr "type" "simd_div") + (if_then_else (match_test "TARGET_CHECK_ZERO_DIV") + (const_int 3) + (const_int 1)) + (not (eq_attr "sync_mem" "none")) (symbol_ref "mips_sync_loop_insns (insn, operands)")] (const_int 1))) @@ -759,7 +765,7 @@ ;; Can the instruction be put into a delay slot? (define_attr "can_delay" "no,yes" - (if_then_else (and (eq_attr "type" "!branch,call,jump") + (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch") (eq_attr "hazard" "none") (match_test "get_attr_insn_count (insn) == 1")) (const_string "yes") @@ -1098,7 +1104,7 @@ ;; Branches that have delay slots and don't have likely variants do ;; not annul on false. -(define_delay (and (eq_attr "type" "branch") +(define_delay (and (eq_attr "type" "branch,simd_branch") (not (match_test "TARGET_MIPS16")) (ior (match_test "TARGET_CB_NEVER") (and (eq_attr "compact_form" "maybe") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 32d6223..fc275fa 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-11-19 Dragan Mladjenovic <dmladjenovic@wavecomp.com> + + * gcc.target/mips/msa-ds.c: New test. + 2019-11-19 Richard Sandiford <richard.sandiford@arm.com> gcc/ Revert: diff --git a/gcc/testsuite/gcc.target/mips/msa-ds.c b/gcc/testsuite/gcc.target/mips/msa-ds.c new file mode 100644 index 0000000..c6932b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-ds.c @@ -0,0 +1,31 @@ +/* { dg-options "-mmsa -mfp64 -mhard-float" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Check that delay slots for MSA branches are filled. */ + +typedef unsigned v4si __attribute__ ((vector_size (16))); + +int __attribute__ ((cold)) foo (v4si v , int a, int b) +{ + int c = 0xf0f0f0f0; + int f = __builtin_msa_bnz_w (v); + + if (f) + return a + c; + else + return b + c; +} + +int __attribute__ ((cold)) bar (v4si v , int a, int b) +{ + int c = 0xf0f0f0f0; + int f = __builtin_msa_bz_w (v); + + if (f) + return a + c; + else + return b + c; +} + +/* { dg-final { scan-assembler-not "foo:.*nop.*jr.*foo," } } */ +/* { dg-final { scan-assembler-not "bar:.*nop.*jr.*bar," } } */ |