diff options
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 38 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr71549.c | 24 |
4 files changed, 76 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9069308..26e8057 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-06-21 H.J. Lu <hongjiu.lu@intel.com> + Ilya Enkovich <ilya.enkovich@intel.com> + + PR target/71549 + * config/i386/i386.c (timode_scalar_chain::fix_debug_reg_uses): + New member function to convert V1TImode register to SUBREG + TImode in debug insn. + (timode_scalar_chain::convert_insn): Call fix_debug_reg_uses + after changing register mode to V1TImode. + 2016-06-21 Virendra Pathak <virendra.pathak@broadcom.com> * config/aarch64/aarch64-cores.def (vulcan): New core. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 91cc0d2..17664ff 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3139,6 +3139,7 @@ class timode_scalar_chain : public scalar_chain private: void mark_dual_mode_def (df_ref def); + void fix_debug_reg_uses (rtx reg); void convert_insn (rtx_insn *insn); /* We don't convert registers to difference size. */ void convert_registers () {} @@ -3790,6 +3791,39 @@ dimode_scalar_chain::convert_insn (rtx_insn *insn) df_insn_rescan (insn); } +/* Fix uses of converted REG in debug insns. */ + +void +timode_scalar_chain::fix_debug_reg_uses (rtx reg) +{ + if (!flag_var_tracking) + return; + + df_ref ref; + for (ref = DF_REG_USE_CHAIN (REGNO (reg)); + ref; + ref = DF_REF_NEXT_REG (ref)) + { + rtx_insn *insn = DF_REF_INSN (ref); + if (DEBUG_INSN_P (insn)) + { + /* It may be a debug insn with a TImode variable in + register. */ + rtx val = PATTERN (insn); + if (GET_MODE (val) != TImode) + continue; + gcc_assert (GET_CODE (val) == VAR_LOCATION); + rtx loc = PAT_VAR_LOCATION_LOC (val); + gcc_assert (REG_P (loc) + && GET_MODE (loc) == V1TImode); + /* Convert V1TImode register, which has been updated by a SET + insn before, to SUBREG TImode. */ + PAT_VAR_LOCATION_LOC (val) = gen_rtx_SUBREG (TImode, loc, 0); + df_insn_rescan (insn); + } + } +} + /* Convert INSN from TImode to V1T1mode. */ void @@ -3806,8 +3840,10 @@ timode_scalar_chain::convert_insn (rtx_insn *insn) rtx tmp = find_reg_equal_equiv_note (insn); if (tmp) PUT_MODE (XEXP (tmp, 0), V1TImode); + PUT_MODE (dst, V1TImode); + fix_debug_reg_uses (dst); } - /* FALLTHRU */ + break; case MEM: PUT_MODE (dst, V1TImode); break; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0131e53..cfee40b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-06-21 H.J. Lu <hongjiu.lu@intel.com> + + PR target/71549 + * gcc.target/i386/pr71549.c: New test. + 2016-06-21 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vadsdu-0.c: Replace diff --git a/gcc/testsuite/gcc.target/i386/pr71549.c b/gcc/testsuite/gcc.target/i386/pr71549.c new file mode 100644 index 0000000..8aac891 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71549.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -g" } */ + +struct S1 +{ + int f0; + int f1; + int f2; + int:4; +} a, b; + +void +fn1 (struct S1 p1) +{ + a = p1; + int c = p1.f0; +} + +int +main () +{ + fn1 (b); + return 0; +} |