diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 17 |
2 files changed, 22 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5def5bd..2a7df9e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2010-12-09 Yao Qi <yao@codesourcery.com> + + * config/arm/arm.c (arm_preferred_rename_class): Implement targethook + PREFERRED_RENAME_CLASS. + 2010-12-08 Ian Lance Taylor <iant@google.com> * doc/sourcebuild.texi (Front End): Remove reference to diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9d2c6dd..ac25365 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -248,6 +248,7 @@ static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, int misalignment, bool is_packed); static void arm_conditional_register_usage (void); +static reg_class_t arm_preferred_rename_class (reg_class_t class); /* Table of machine attributes. */ @@ -585,6 +586,10 @@ static const struct default_options arm_option_optimization_table[] = #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ arm_builtin_support_vector_misalignment +#undef TARGET_PREFERRED_RENAME_CLASS +#define TARGET_PREFERRED_RENAME_CLASS \ + arm_preferred_rename_class + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -23467,4 +23472,16 @@ arm_conditional_register_usage (void) SUBTARGET_CONDITIONAL_REGISTER_USAGE } +static reg_class_t +arm_preferred_rename_class (reg_class_t class) +{ + /* Thumb-2 instructions using LO_REGS may be smaller than instructions + using GENERIC_REGS. During register rename pass, we prefer LO_REGS, + and code size can be reduced. */ + if (TARGET_THUMB2 && class == GENERAL_REGS) + return LO_REGS; + else + return NO_REGS; +} + #include "gt-arm.h" |