diff options
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/ia64/sync.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/ia64/sync-1.c | 23 |
4 files changed, 43 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f4da0b9..408250b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,13 @@ 2009-03-27 H.J. Lu <hongjiu.lu@intel.com> + Jakub Jelinek <jakub@redhat.com> + + PR target/38034 + * config/ia64/sync.md (cmpxchg_rel_<mode>): Replace input + gr_register_operand with gr_reg_or_0_operand. + (cmpxchg_rel_di): Likewise. + (sync_lock_test_and_set<mode>): Likewise. + +2009-03-27 H.J. Lu <hongjiu.lu@intel.com> * jump.c (rtx_renumbered_equal_p): Use subreg_get_info. (true_regnum): Likewise. diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md index e356081..b40e208 100644 --- a/gcc/config/ia64/sync.md +++ b/gcc/config/ia64/sync.md @@ -151,10 +151,10 @@ (unspec:I124MODE [(match_dup 1) (match_operand:DI 2 "ar_ccv_reg_operand" "") - (match_operand:I124MODE 3 "gr_register_operand" "r")] + (match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")] UNSPEC_CMPXCHG_ACQ))] "" - "cmpxchg<modesuffix>.rel %0 = %1, %3, %2" + "cmpxchg<modesuffix>.rel %0 = %1, %r3, %2" [(set_attr "itanium_class" "sem")]) (define_insn "cmpxchg_rel_di" @@ -163,19 +163,19 @@ (set (match_dup 1) (unspec:DI [(match_dup 1) (match_operand:DI 2 "ar_ccv_reg_operand" "") - (match_operand:DI 3 "gr_register_operand" "r")] + (match_operand:DI 3 "gr_reg_or_0_operand" "rO")] UNSPEC_CMPXCHG_ACQ))] "" - "cmpxchg8.rel %0 = %1, %3, %2" + "cmpxchg8.rel %0 = %1, %r3, %2" [(set_attr "itanium_class" "sem")]) (define_insn "sync_lock_test_and_set<mode>" [(set (match_operand:IMODE 0 "gr_register_operand" "=r") (match_operand:IMODE 1 "not_postinc_memory_operand" "+S")) (set (match_dup 1) - (match_operand:IMODE 2 "gr_register_operand" "r"))] + (match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))] "" - "xchg<modesuffix> %0 = %1, %2" + "xchg<modesuffix> %0 = %1, %r2" [(set_attr "itanium_class" "sem")]) (define_expand "sync_lock_release<mode>" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a67ad29..0060483 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2009-03-27 H.J. Lu <hongjiu.lu@intel.com> + PR target/38034 + * gcc.target/ia64/sync-1.c: New. + +2009-03-27 H.J. Lu <hongjiu.lu@intel.com> + PR target/39472 * gcc.target/x86_64/abi/callabi/func-2a.c: New. * gcc.target/x86_64/abi/callabi/func-2b.c: Likewise. diff --git a/gcc/testsuite/gcc.target/ia64/sync-1.c b/gcc/testsuite/gcc.target/ia64/sync-1.c new file mode 100644 index 0000000..95f6dae --- /dev/null +++ b/gcc/testsuite/gcc.target/ia64/sync-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "xchg4 .*, r0" } } */ +/* { dg-final { scan-assembler "cmpxchg4.*, r0, .*" } } */ +/* { dg-final { scan-assembler "cmpxchg8.*, r0, .*" } } */ + +int +foo1 (int *p) +{ + return __sync_lock_test_and_set (p, 0); +} + +int +foo2 (int *p, int v) +{ + return __sync_bool_compare_and_swap (p, v, 0); +} + +long +foo3 (long *p, long v) +{ + return __sync_bool_compare_and_swap (p, v, 0); +} |