diff options
| -rw-r--r-- | gcc/config/aarch64/atomics.md | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ldar_2.c | 27 |
2 files changed, 44 insertions, 0 deletions
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 9048700..bc95f6d 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -640,6 +640,23 @@ } ) +(define_insn "*atomic_load<ALLX:mode>_zext<SD_HSDI:mode>" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r") + (zero_extend:SD_HSDI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDA)))] + "GET_MODE_SIZE (<SD_HSDI:MODE>mode) > GET_MODE_SIZE (<ALLX:MODE>mode)" + { + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) + return "ldr<ALLX:atomic_sfx>\t%<ALLX:w>0, %1"; + else + return "ldar<ALLX:atomic_sfx>\t%<ALLX:w>0, %1"; + } +) + (define_insn "atomic_load<mode>" [(set (match_operand:ALLI 0 "register_operand" "=r") (unspec_volatile:ALLI diff --git a/gcc/testsuite/gcc.target/aarch64/ldar_2.c b/gcc/testsuite/gcc.target/aarch64/ldar_2.c new file mode 100644 index 0000000..60b0717 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldar_2.c @@ -0,0 +1,27 @@ +/* Test that the zero-extending patterns for LDAR are used. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <stdint.h> + +uint8_t v_uint8_t; +uint16_t v_uint16_t; +uint32_t v_uint32_t; +uint64_t v_uint64_t; + +#define FUNC(FROM, TO) \ +TO \ +load_##FROM##_ext_##TO (void) \ +{ \ + return __atomic_load_n (&v_##FROM, __ATOMIC_ACQUIRE); \ +} + +FUNC (uint8_t, uint16_t) +FUNC (uint8_t, uint32_t) +FUNC (uint8_t, uint64_t) +FUNC (uint16_t, uint32_t) +FUNC (uint16_t, uint64_t) +FUNC (uint32_t, uint64_t) + +/* { dg-final { scan-assembler-not {and\tw[0-9+], w[0-9]+, 255} } } */ +/* { dg-final { scan-assembler-not {uxtw\tx[0-9+], w[0-9]+} } } */ |