diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/s390/vector.md | 52 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c | 26 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c | 26 |
5 files changed, 115 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98a8f47..622e024 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-12-21 Andreas Krebbel <krebbel@linux.ibm.com> + + * config/s390/vector.md ("floatv2div2df2", "floatunsv2div2df2") + ("fix_truncv2dfv2di2", "fixuns_truncv2dfv2di2"): New pattern + definitions. + 2018-12-21 Eric Botcazou <ebotcazou@adacore.com> PR rtl-optimization/87727 diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index f0e4049..4c84505 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1960,6 +1960,58 @@ operands[6] = gen_reg_rtx (V16QImode); }) +; +; BFP <-> integer conversions +; + +; signed integer to floating point + +; op2: inexact exception not suppressed (IEEE 754 2008) +; op3: according to current rounding mode + +(define_insn "floatv2div2df2" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (float:V2DF (match_operand:V2DI 1 "register_operand" "v")))] + "TARGET_VX" + "vcdgb\t%v0,%v1,0,0" + [(set_attr "op_type" "VRR")]) + +; unsigned integer to floating point + +; op2: inexact exception not suppressed (IEEE 754 2008) +; op3: according to current rounding mode + +(define_insn "floatunsv2div2df2" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unsigned_float:V2DF (match_operand:V2DI 1 "register_operand" "v")))] + "TARGET_VX" + "vcdlgb\t%v0,%v1,0,0" + [(set_attr "op_type" "VRR")]) + +; floating point to signed integer + +; op2: inexact exception not suppressed (IEEE 754 2008) +; op3: rounding mode 5 (round towards 0 C11 6.3.1.4) + +(define_insn "fix_truncv2dfv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (fix:V2DI (match_operand:V2DF 1 "register_operand" "v")))] + "TARGET_VX" + "vcgdb\t%v0,%v1,0,5" + [(set_attr "op_type" "VRR")]) + +; floating point to unsigned integer + +; op2: inexact exception not suppressed (IEEE 754 2008) +; op3: rounding mode 5 (round towards 0 C11 6.3.1.4) + +(define_insn "fixuns_truncv2dfv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unsigned_fix:V2DI (match_operand:V2DF 1 "register_operand" "v")))] + "TARGET_VX" + "vclgdb\t%v0,%v1,0,5" + [(set_attr "op_type" "VRR")]) + ; reduc_smin ; reduc_smax ; reduc_umin diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 76ffd3d..7889c08 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-12-21 Andreas Krebbel <krebbel@linux.ibm.com> + + * gcc.target/s390/vector/fp-signedint-convert-1.c: New test. + * gcc.target/s390/vector/fp-unsignedint-convert-1.c: New test. + 2018-12-21 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/88563 diff --git a/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c b/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c new file mode 100644 index 0000000..536817a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c @@ -0,0 +1,26 @@ +/* { dg-compile } */ +/* { dg-options "-O3 -march=z13 -mzarch" } */ + +typedef long long __attribute__((vector_size(16))) v2di; +typedef double __attribute__((vector_size(16))) v2df; + +v2di longvec; +v2df doublevec; + +v2di +tolong (v2df a) +{ + v2di out = (v2di){ (long long)a[0], (long long)a[1] }; + return out; +} + +/* { dg-final { scan-assembler-times "vcgdb\t%v24,%v24,0,5" 1 } } */ + +v2df +todouble (v2di a) +{ + v2df out = (v2df){ (double)a[0], (double)a[1] }; + return out; +} + +/* { dg-final { scan-assembler-times "vcdgb\t%v24,%v24,0,0" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c b/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c new file mode 100644 index 0000000..61409bc --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c @@ -0,0 +1,26 @@ +/* { dg-compile } */ +/* { dg-options "-O3 -march=z13 -mzarch" } */ + +typedef unsigned long long __attribute__((vector_size(16))) v2di; +typedef double __attribute__((vector_size(16))) v2df; + +v2di longvec; +v2df doublevec; + +v2di +toulong (v2df a) +{ + v2di out = (v2di){ (unsigned long long)a[0], (unsigned long long)a[1] }; + return out; +} + +/* { dg-final { scan-assembler-times "vclgdb\t%v24,%v24,0,5" 1 } } */ + +v2df +todouble (v2di a) +{ + v2df out = (v2df){ (double)a[0], (double)a[1] }; + return out; +} + +/* { dg-final { scan-assembler-times "vcdlgb\t%v24,%v24,0,0" 1 } } */ |