diff options
| -rw-r--r-- | gcc/ira.c | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr97684.c | 24 |
2 files changed, 33 insertions, 3 deletions
@@ -5566,6 +5566,15 @@ ira (FILE *f) if (warn_clobbered) generate_setjmp_warnings (); + /* update_equiv_regs can use reg classes of pseudos and they are set up in + register pressure sensitive scheduling and loop invariant motion and in + live range shrinking. This info can become obsolete if we add new pseudos + since the last set up. Recalculate it again if the new pseudos were + added. */ + if (resize_reg_info () && (flag_sched_pressure || flag_live_range_shrinkage + || flag_ira_loop_pressure)) + ira_set_pseudo_classes (true, ira_dump_file); + init_alias_analysis (); loop_optimizer_init (AVOID_CFG_MODIFICATIONS); reg_equiv = XCNEWVEC (struct equivalence, max_reg_num ()); @@ -5610,9 +5619,6 @@ ira (FILE *f) regstat_recompute_for_max_regno (); } - if (resize_reg_info () && flag_ira_loop_pressure) - ira_set_pseudo_classes (true, ira_dump_file); - setup_reg_equiv (); grow_reg_equivs (); setup_reg_equiv_init (); diff --git a/gcc/testsuite/gcc.target/i386/pr97684.c b/gcc/testsuite/gcc.target/i386/pr97684.c new file mode 100644 index 0000000..983bf53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr97684.c @@ -0,0 +1,24 @@ +/* PR rtl-optimization/97684 */ +/* { dg-do compile } */ +/* { dg-options "-O1 -flive-range-shrinkage -fschedule-insns -fselective-scheduling -funroll-all-loops -fno-web" } */ + +void +c5 (double); + +void +g4 (int *n4) +{ + double lp = 0.0; + int fn; + + for (fn = 0; fn < 18; ++fn) + { + int as; + + as = __builtin_abs (n4[fn]); + if (as > lp) + lp = as; + } + + c5 (lp); +} |