diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 33 |
2 files changed, 38 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 32075f6..988a860 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-05-17 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (isa): New attribute. + (enabled): New attribute. + 2019-05-17 Max Filippov <jcmvbkbc@gmail.com> * config/aarch64/aarch64.c (aarch64_output_mi_thunk): Call diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 31fc90a..0906ccb 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -265,6 +265,39 @@ rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) +;; The ISA we implement. +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any")) + +;; Is this alternative enabled for the current CPU/ISA/etc.? +(define_attr "enabled" "" + (cond + [(eq_attr "isa" "any") + (const_int 1) + + (and (eq_attr "isa" "p5") + (match_test "TARGET_POPCNTB")) + (const_int 1) + + (and (eq_attr "isa" "p6") + (match_test "TARGET_CMPB")) + (const_int 1) + + (and (eq_attr "isa" "p7") + (match_test "TARGET_POPCNTD")) + (const_int 1) + + (and (eq_attr "isa" "p7v") + (match_test "TARGET_VSX")) + (const_int 1) + + (and (eq_attr "isa" "p8v") + (match_test "TARGET_P8_VECTOR")) + (const_int 1) + + (and (eq_attr "isa" "p9v") + (match_test "TARGET_P9_VECTOR")) + (const_int 1) + ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded |