diff options
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 26 |
2 files changed, 26 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ff14980..a3f8471 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,19 @@ Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/i386/sse.md + (define_insn "<sse2_avx2>_packsswb<mask_name>"): Add masking. + (define_insn "<sse2_avx2>_packuswb<mask_name>"): Ditto. + +2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + + * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512. (define_insn "avx512bw_pmaddubsw512<mode><mask_name>"): New. (define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>"): diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a71f969..2673ddf 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10840,21 +10840,21 @@ DONE; }) -(define_insn "<sse2_avx2>_packsswb" - [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x") +(define_insn "<sse2_avx2>_packsswb<mask_name>" + [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,v") (vec_concat:VI1_AVX2 (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,x")) + (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,xm"))))] - "TARGET_SSE2" + (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packsswb\t{%2, %0|%0, %2} - vpacksswb\t{%2, %1, %0|%0, %1, %2}" + vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "<sseinsnmode>")]) (define_insn "<sse2_avx2>_packssdw" @@ -10874,17 +10874,17 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<sse2_avx2>_packuswb" - [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x") +(define_insn "<sse2_avx2>_packuswb<mask_name>" + [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,v") (vec_concat:VI1_AVX2 (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,x")) + (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,xm"))))] - "TARGET_SSE2" + (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packuswb\t{%2, %0|%0, %2} - vpackuswb\t{%2, %1, %0|%0, %1, %2}" + vpackuswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*") |