diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/znver1.md | 90 |
2 files changed, 50 insertions, 45 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7c0f325..115d778 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-03-18 Venkataramanan Kumar <venkataramanan.kumar@amd.com> + + * config/i386/znver1.md : Fix latencies of FP/SSE/AVX + load type reservations. + 2016-03-17 John David Anglin <danglin@gcc.gnu.org> PR target/70188 diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index 1d28c05..7db0562 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -328,7 +328,7 @@ (eq_attr "type" "fcmov")) "znver1-vector,znver1-fvector") -(define_insn_reservation "znver1_fp_mov_direct_load" 5 +(define_insn_reservation "znver1_fp_mov_direct_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "znver1_decode" "direct") (and (eq_attr "type" "fmov") @@ -349,7 +349,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp3") -(define_insn_reservation "znver1_fp_mov_double_load" 9 +(define_insn_reservation "znver1_fp_mov_double_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "fmov") @@ -386,7 +386,7 @@ (eq_attr "type" "fcmp")))) "znver1-double,znver1-fp0,znver1-fp2") -(define_insn_reservation "znver1_fp_fcmp_load" 6 +(define_insn_reservation "znver1_fp_fcmp_load" 9 (and (eq_attr "cpu" "znver1") (and (eq_attr "memory" "none") (and (eq_attr "znver1_decode" "double") @@ -400,13 +400,13 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0*5") -(define_insn_reservation "znver1_fp_op_mul_load" 9 +(define_insn_reservation "znver1_fp_op_mul_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp0*5") -(define_insn_reservation "znver1_fp_op_imul_load" 13 +(define_insn_reservation "znver1_fp_op_imul_load" 16 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fop,fmul") (and (eq_attr "fp_int_src" "true") @@ -419,13 +419,13 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3*15") -(define_insn_reservation "znver1_fp_op_div_load" 19 +(define_insn_reservation "znver1_fp_op_div_load" 22 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fdiv") (eq_attr "memory" "load"))) "znver1-direct,znver1-load,znver1-fp3*15") -(define_insn_reservation "znver1_fp_op_idiv_load" 24 +(define_insn_reservation "znver1_fp_op_idiv_load" 27 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") @@ -444,7 +444,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") -(define_insn_reservation "znver1_mmx_add_load" 5 +(define_insn_reservation "znver1_mmx_add_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "mmxadd") (eq_attr "memory" "load"))) @@ -456,7 +456,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0|znver1-fp3") -(define_insn_reservation "znver1_mmx_cmp_load" 5 +(define_insn_reservation "znver1_mmx_cmp_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "mmxcmp") (eq_attr "memory" "load"))) @@ -468,7 +468,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp1|znver1-fp2") -(define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 5 +(define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") (eq_attr "memory" "load"))) @@ -480,7 +480,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp2") -(define_insn_reservation "znver1_mmx_shift_move_load" 5 +(define_insn_reservation "znver1_mmx_shift_move_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "mmxshft,mmxmov") (eq_attr "memory" "load"))) @@ -498,7 +498,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp0*3") -(define_insn_reservation "znver1_mmx_load" 7 +(define_insn_reservation "znver1_mmx_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "load"))) @@ -511,7 +511,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fpu") -(define_insn_reservation "znver1_avx256_log_load" 5 +(define_insn_reservation "znver1_avx256_log_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF,OI") (and (eq_attr "type" "sselog") @@ -524,7 +524,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fpu") -(define_insn_reservation "znver1_sse_log_load" 5 +(define_insn_reservation "znver1_sse_log_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "sselog") (eq_attr "memory" "load"))) @@ -537,7 +537,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp1|znver1-fp2") -(define_insn_reservation "znver1_avx256_log1_load" 5 +(define_insn_reservation "znver1_avx256_log1_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF,OI") (and (eq_attr "type" "sselog1") @@ -550,7 +550,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp1|znver1-fp2") -(define_insn_reservation "znver1_sse_log1_load" 5 +(define_insn_reservation "znver1_sse_log1_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "sselog1") (eq_attr "memory" "!none"))) @@ -565,7 +565,7 @@ (eq_attr "memory" "none")))))) "znver1-direct,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_sse_comi_load" 5 +(define_insn_reservation "znver1_sse_comi_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF") (and (eq_attr "prefix" "!vex") @@ -583,7 +583,7 @@ (eq_attr "memory" "none")))))) "znver1-double,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_sse_comi_double_load" 7 +(define_insn_reservation "znver1_sse_comi_double_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4SF,V2DF,TI") (and (eq_attr "prefix" "vex") @@ -600,7 +600,7 @@ (eq_attr "memory" "none"))))) "znver1-direct,znver1-fp1|znver1-fp2") -(define_insn_reservation "znver1_sse_test_load" 5 +(define_insn_reservation "znver1_sse_test_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") (and (eq_attr "prefix_extra" "1") @@ -642,7 +642,7 @@ (eq_attr "memory" "store")))) "znver1-direct,znver1-fpu,znver1-store") -(define_insn_reservation "znver1_sseavx_mov_load" 5 +(define_insn_reservation "znver1_sseavx_mov_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") (and (eq_attr "type" "ssemov") @@ -663,7 +663,7 @@ (eq_attr "memory" "store")))) "znver1-double,znver1-fpu,znver1-store") -(define_insn_reservation "znver1_avx256_mov_load" 5 +(define_insn_reservation "znver1_avx256_mov_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF,OI") (and (eq_attr "type" "ssemov") @@ -678,7 +678,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp2|znver1-fp3") -(define_insn_reservation "znver1_sseavx_add_load" 7 +(define_insn_reservation "znver1_sseavx_add_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") (and (eq_attr "type" "sseadd") @@ -692,7 +692,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp2|znver1-fp3") -(define_insn_reservation "znver1_avx256_add_load" 7 +(define_insn_reservation "znver1_avx256_add_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF,OI") (and (eq_attr "type" "sseadd") @@ -706,7 +706,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_sseavx_fma_load" 9 +(define_insn_reservation "znver1_sseavx_fma_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF") (and (eq_attr "type" "ssemuladd") @@ -720,7 +720,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_avx256_fma_load" 9 +(define_insn_reservation "znver1_avx256_fma_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF") (and (eq_attr "type" "ssemuladd") @@ -734,7 +734,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") -(define_insn_reservation "znver1_sseavx_iadd_load" 5 +(define_insn_reservation "znver1_sseavx_iadd_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "DI,TI") (and (eq_attr "type" "sseiadd") @@ -748,7 +748,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3") -(define_insn_reservation "znver1_avx256_iadd_load" 5 +(define_insn_reservation "znver1_avx256_iadd_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseiadd") @@ -756,7 +756,7 @@ "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") ;; SSE conversions. -(define_insn_reservation "znver1_ssecvtsf_si_load" 9 +(define_insn_reservation "znver1_ssecvtsf_si_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SI") (and (eq_attr "type" "sseicvt") @@ -772,7 +772,7 @@ (eq_attr "memory" "none"))))) "znver1-double,znver1-fp3,znver1-ieu0") -(define_insn_reservation "znver1_ssecvtdf_si_load" 9 +(define_insn_reservation "znver1_ssecvtdf_si_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SI") (and (eq_attr "type" "sseicvt") @@ -789,7 +789,7 @@ (eq_attr "memory" "none"))) "znver1-direct,znver1-fp3") -(define_insn_reservation "znver1_ssecvt_load" 8 +(define_insn_reservation "znver1_ssecvt_load" 11 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "ssecvt") (eq_attr "memory" "load"))) @@ -803,7 +803,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp3*10") -(define_insn_reservation "znver1_ssediv_ss_ps_load" 14 +(define_insn_reservation "znver1_ssediv_ss_ps_load" 17 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4SF,SF") (and (eq_attr "type" "ssediv") @@ -817,7 +817,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp3*13") -(define_insn_reservation "znver1_ssediv_sd_pd_load" 17 +(define_insn_reservation "znver1_ssediv_sd_pd_load" 20 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V2DF,DF") (and (eq_attr "type" "ssediv") @@ -831,7 +831,7 @@ (eq_attr "type" "ssediv")))) "znver1-double,znver1-fp3*12") -(define_insn_reservation "znver1_ssediv_avx256_ps_load" 16 +(define_insn_reservation "znver1_ssediv_avx256_ps_load" 19 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssediv") @@ -845,7 +845,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp3*15") -(define_insn_reservation "znver1_ssediv_avx256_pd_load" 18 +(define_insn_reservation "znver1_ssediv_avx256_pd_load" 22 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssediv") @@ -859,7 +859,7 @@ (eq_attr "memory" "none")))) "znver1-direct,(znver1-fp0|znver1-fp1)*3") -(define_insn_reservation "znver1_ssemul_ss_ps_load" 7 +(define_insn_reservation "znver1_ssemul_ss_ps_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4SF,SF") (and (eq_attr "type" "ssemul") @@ -873,7 +873,7 @@ (eq_attr "memory" "none")))) "znver1-double,(znver1-fp0|znver1-fp1)*3") -(define_insn_reservation "znver1_ssemul_avx256_ps_load" 7 +(define_insn_reservation "znver1_ssemul_avx256_ps_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssemul") @@ -887,7 +887,7 @@ (eq_attr "memory" "none")))) "znver1-direct,(znver1-fp0|znver1-fp1)*4") -(define_insn_reservation "znver1_ssemul_sd_pd_load" 8 +(define_insn_reservation "znver1_ssemul_sd_pd_load" 11 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V2DF,DF") (and (eq_attr "type" "ssemul") @@ -902,7 +902,7 @@ (eq_attr "memory" "none"))))) "znver1-double,(znver1-fp0|znver1-fp1)*4") -(define_insn_reservation "znver1_ssemul_avx256_pd_load" 8 +(define_insn_reservation "znver1_ssemul_avx256_pd_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssemul") @@ -924,14 +924,14 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp0*4") -(define_insn_reservation "znver1_sseimul_load" 7 +(define_insn_reservation "znver1_sseimul_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "TI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "load")))) "znver1-direct,znver1-load,znver1-fp0*3") -(define_insn_reservation "znver1_sseimul_avx256_load" 8 +(define_insn_reservation "znver1_sseimul_avx256_load" 11 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseimul") @@ -945,7 +945,7 @@ (eq_attr "type" "sseimul")))) "znver1-direct,znver1-fp0*3") -(define_insn_reservation "znver1_sseimul_load_di" 7 +(define_insn_reservation "znver1_sseimul_load_di" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "DI") (and (eq_attr "type" "sseimul") @@ -960,7 +960,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_sse_cmp_load" 5 +(define_insn_reservation "znver1_sse_cmp_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "SF,DF,V4SF,V2DF") (and (eq_attr "type" "ssecmp") @@ -974,7 +974,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp0|znver1-fp1") -(define_insn_reservation "znver1_sse_cmp_avx256_load" 5 +(define_insn_reservation "znver1_sse_cmp_avx256_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF,V4DF") (and (eq_attr "type" "ssecmp") @@ -988,7 +988,7 @@ (eq_attr "memory" "none")))) "znver1-direct,znver1-fp0|znver1-fp3") -(define_insn_reservation "znver1_sse_icmp_load" 5 +(define_insn_reservation "znver1_sse_icmp_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "QI,HI,SI,DI,TI") (and (eq_attr "type" "ssecmp") @@ -1002,7 +1002,7 @@ (eq_attr "memory" "none")))) "znver1-double,znver1-fp0|znver1-fp3") -(define_insn_reservation "znver1_sse_icmp_avx256_load" 5 +(define_insn_reservation "znver1_sse_icmp_avx256_load" 8 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "OI") (and (eq_attr "type" "ssecmp") |