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| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/combine-2-2.c | 17 |
2 files changed, 22 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3850aaa..0731143 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-07-30 Segher Boessenkool <segher@kernel.crashing.org> + + PR rtl-optimization/85160 + * gcc.target/powerpc/combine-2-2.c: New testcase. + 2018-07-27 Martin Sebor <msebor@redhat.com> PR tree-optimization/86696 diff --git a/gcc/testsuite/gcc.target/powerpc/combine-2-2.c b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c new file mode 100644 index 0000000..234476d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-O2" } */ + +/* PR85160 */ + +/* Originally, the "x >> 14" are CSEd away (eventually becoming a srawi + instruction), and the two ANDs remain separate instructions because + combine cannot deal with this. + + Now that combine knows how to combine two RTL insns into two, it manages + to make this just the sum of two rlwinm instructions. */ + +int f(int x) +{ + return ((x >> 14) & 6) + ((x >> 14) & 4); +} + +/* { dg-final { scan-assembler-not {\msrawi\M} } } */ |