diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/altivec-20.c | 23 |
3 files changed, 29 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 59b1dce..36d0804 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2005-02-24 Fariborz Jahanian <fjahanian@apple.com> + + * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Check for + vector types if to use base reg for misaligned non-word ld/std. + 2005-02-24 Hans-Peter Nilsson <hp@axis.com> PR target/14619 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ea5c010..e07ac50 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3881,6 +3881,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) && GET_CODE (XEXP (x, 1)) == CONST_INT && (INTVAL (XEXP (x, 1)) & 3) != 0 + && !ALTIVEC_VECTOR_MODE (mode) && GET_MODE_SIZE (mode) >= UNITS_PER_WORD && TARGET_POWERPC64) { diff --git a/gcc/testsuite/gcc.dg/altivec-20.c b/gcc/testsuite/gcc.dg/altivec-20.c new file mode 100644 index 0000000..f733d18 --- /dev/null +++ b/gcc/testsuite/gcc.dg/altivec-20.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -mcpu=G5 -O2" } */ + +#include <altivec.h> + +void foo( float scalar) +{ + unsigned long width; + unsigned long x; + vector float vColor; + vector unsigned int selectMask; + vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) ); + + float *destRow; + vector float store, load0; + + for( ; x < width; x++) + { + load0 = vec_sel( vColor, load0, selectMask ); + vec_st( store, 0, destRow ); + store = load0; + } +} |