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-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/mips/mips.h7
2 files changed, 10 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6821951..c6282e0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2007-04-28 Sandra Loosemore <sandra@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * config/mips/mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16.
+
2007-04-28 Jan Hubicka <jh@suse.cz>
* config/alpha/alpha.c (alpha_output_mi_thunk_osf): Use
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7284543..e3c631e 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -2240,8 +2240,11 @@ typedef struct mips_args {
difference in cost between byte and (aligned) word loads.
On RISC machines, it tends to generate better code to define
- this as 1, since it avoids making a QI or HI mode register. */
-#define SLOW_BYTE_ACCESS 1
+ this as 1, since it avoids making a QI or HI mode register.
+
+ But, generating word accesses for -mips16 is generally bad as shifts
+ (often extended) would be needed for byte accesses. */
+#define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */