diff options
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/vector.md | 88 |
3 files changed, 103 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e3bba82..6f5d9cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2012-03-06 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/50310 + * config/rs6000/vector.md (vector_uneq<mode>): Add support for + UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons. + (vector_ltgt<mode>): Likewise. + (vector_ordered<mode>): Likewise. + (vector_unordered<mode>): Likewise. + * config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): + Likewise. + 2012-03-06 Aldy Hernandez <aldyh@redhat.com> * trans-mem.c: New typedef for tm_region_p. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 04ea22b..5558f77 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16077,6 +16077,10 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) case EQ: case GT: case GTU: + case ORDERED: + case UNORDERED: + case UNEQ: + case LTGT: mask = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, mask, diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index bcb23ac..6674054 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -516,6 +516,94 @@ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") +(define_insn_and_split "*vector_uneq<mode>" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (<MODE>mode); + operands[4] = gen_reg_rtx (<MODE>mode); +}") + +(define_insn_and_split "*vector_ltgt<mode>" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (<MODE>mode); + operands[4] = gen_reg_rtx (<MODE>mode); +}") + +(define_insn_and_split "*vector_ordered<mode>" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (<MODE>mode); + operands[4] = gen_reg_rtx (<MODE>mode); +}") + +(define_insn_and_split "*vector_unordered<mode>" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (<MODE>mode); + operands[4] = gen_reg_rtx (<MODE>mode); +}") + ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select_<mode>" |