diff options
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index fd4f1a4..27e2f31 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -103,7 +103,7 @@ Target Mask(SAVE_RESTORE) Use smaller but slower prologue and epilogue code. mshorten-memrefs -Target Bool Var(riscv_mshorten_memrefs) Init(1) +Target Var(riscv_mshorten_memrefs) Init(1) Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more memory accesses to be generated as compressed instructions. Currently targets 32-bit integer load/stores. @@ -134,12 +134,12 @@ Target Mask(EXPLICIT_RELOCS) Use %reloc() operators, rather than assembly macros, to load addresses. mrelax -Target Bool Var(riscv_mrelax) Init(1) +Target Var(riscv_mrelax) Init(1) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. mcsr-check -Target Bool Var(riscv_mcsr_check) Init(0) +Target Var(riscv_mcsr_check) Init(0) Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. @@ -483,15 +483,15 @@ Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1) Always inline subword atomic operations. minline-strcmp -Target Bool Var(riscv_inline_strcmp) Init(0) +Target Var(riscv_inline_strcmp) Init(0) Inline strcmp calls if possible. minline-strncmp -Target Bool Var(riscv_inline_strncmp) Init(0) +Target Var(riscv_inline_strncmp) Init(0) Inline strncmp calls if possible. minline-strlen -Target Bool Var(riscv_inline_strlen) Init(0) +Target Var(riscv_inline_strlen) Init(0) Inline strlen calls if possible. -param=riscv-strcmp-inline-limit= @@ -542,7 +542,7 @@ madjust-lmul-cost Target Var(TARGET_ADJUST_LMUL_COST) Init(0) -param=riscv-vector-abi -Target Undocumented Bool Var(riscv_vector_abi) Init(0) +Target Undocumented Var(riscv_vector_abi) Init(0) Enable the use of vector registers for function arguments and return value. This is an experimental switch and may be subject to change in the future. |