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-rw-r--r--gcc/ChangeLog21
-rw-r--r--gcc/doc/tm.texi14
-rw-r--r--gcc/genattr.c3
-rw-r--r--gcc/genautomata.c39
-rw-r--r--gcc/haifa-sched.c6
-rw-r--r--gcc/target-def.h6
-rw-r--r--gcc/target.h7
7 files changed, 95 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 40b6704..d63047c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2007-08-22 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * target.h (struct gcc_target.sched: dfa_pre_advance_cycle,
+ dfa_post_advance_cycle): New scheduler hooks.
+ * target-def.h (TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE,
+ TARGET_SCHED_DFA_POST_ADVANCE_CYCLE): New macros to initialize
+ new hooks.
+ (TARGET_SCHED): Use them.
+ * doc/tm.texi (TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE,
+ TARGET_SCHED_DFA_POST_ADVANCE_CYCLE): Document new hooks.
+ * haifa-sched.c (advance_one_cycle): Invoke new hooks.
+
+ * genautomata.c (insn_has_dfa_reservation_p): New DFA interface
+ function to facilitate debugging.
+ (INSN_HAS_DFA_RESERVATION_P_FUNC_NAME): New macro.
+ (output_insn_has_dfa_reservation_p): New static function to output
+ insn_has_dfa_reservation_p ().
+ (write_automata): Use it.
+ * genattr.c (main): Output declaration for
+ insn_has_dfa_reservation_p ().
+
2007-08-22 Christian Bruel <christian.bruel@st.com>
Richard Guenther <rguenther@suse.de>
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 2079ccb..0ec10c5 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -6180,6 +6180,20 @@ The hook is analogous to @samp{TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN} but
used to initialize data used by the previous hook.
@end deftypefn
+@deftypefn {Target Hook} void TARGET_SCHED_DFA_PRE_CYCLE_ADVANCE (void)
+The hook to notify target that the current simulated cycle is about to finish.
+The hook is analogous to @samp{TARGET_SCHED_DFA_PRE_CYCLE_INSN} but used
+to change the state in more complicated situations - e.g. when advancing
+state on a single insn is not enough.
+@end deftypefn
+
+@deftypefn {Target Hook} void TARGET_SCHED_DFA_POST_CYCLE_ADVANCE (void)
+The hook to notify target that new simulated cycle has just started.
+The hook is analogous to @samp{TARGET_SCHED_DFA_POST_CYCLE_INSN} but used
+to change the state in more complicated situations - e.g. when advancing
+state on a single insn is not enough.
+@end deftypefn
+
@deftypefn {Target Hook} int TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD (void)
This hook controls better choosing an insn from the ready insn queue
for the @acronym{DFA}-based insn scheduler. Usually the scheduler
diff --git a/gcc/genattr.c b/gcc/genattr.c
index 9206abe..8ff3cd3 100644
--- a/gcc/genattr.c
+++ b/gcc/genattr.c
@@ -244,6 +244,9 @@ main (int argc, char **argv)
printf (" DFA state. */\n");
printf ("extern int cpu_unit_reservation_p (state_t, int);\n");
printf ("#endif\n\n");
+ printf ("/* The following function returns true if insn\n");
+ printf (" has a dfa reservation. */\n");
+ printf ("extern bool insn_has_dfa_reservation_p (rtx);\n\n");
printf ("/* Clean insn code cache. It should be called if there\n");
printf (" is a chance that condition value in a\n");
printf (" define_insn_reservation will be changed after\n");
diff --git a/gcc/genautomata.c b/gcc/genautomata.c
index 5657a0d..96737bc 100644
--- a/gcc/genautomata.c
+++ b/gcc/genautomata.c
@@ -6859,6 +6859,8 @@ output_reserved_units_table_name (FILE *f, automaton_t automaton)
#define CPU_UNIT_RESERVATION_P_FUNC_NAME "cpu_unit_reservation_p"
+#define INSN_HAS_DFA_RESERVATION_P_FUNC_NAME "insn_has_dfa_reservation_p"
+
#define DFA_CLEAN_INSN_CACHE_FUNC_NAME "dfa_clean_insn_cache"
#define DFA_CLEAR_SINGLE_INSN_CACHE_FUNC_NAME "dfa_clear_single_insn_cache"
@@ -8346,6 +8348,42 @@ output_cpu_unit_reservation_p (void)
fprintf (output_file, " return 0;\n}\n\n");
}
+/* The following function outputs a function to check if insn
+ has a dfa reservation. */
+static void
+output_insn_has_dfa_reservation_p (void)
+{
+ fprintf (output_file,
+ "bool\n%s (rtx %s ATTRIBUTE_UNUSED)\n{\n",
+ INSN_HAS_DFA_RESERVATION_P_FUNC_NAME,
+ INSN_PARAMETER_NAME);
+
+ if (DECL_INSN_RESERV (advance_cycle_insn_decl)->insn_num == 0)
+ {
+ fprintf (output_file, " return false;\n}\n\n");
+ return;
+ }
+
+ fprintf (output_file, " int %s;\n\n", INTERNAL_INSN_CODE_NAME);
+
+ fprintf (output_file, " if (%s == 0)\n %s = %s;\n",
+ INSN_PARAMETER_NAME,
+ INTERNAL_INSN_CODE_NAME, ADVANCE_CYCLE_VALUE_NAME);
+ fprintf (output_file, " else\n\
+ {\n\
+ %s = %s (%s);\n\
+ if (%s > %s)\n\
+ %s = %s;\n\
+ }\n\n",
+ INTERNAL_INSN_CODE_NAME, DFA_INSN_CODE_FUNC_NAME,
+ INSN_PARAMETER_NAME,
+ INTERNAL_INSN_CODE_NAME, ADVANCE_CYCLE_VALUE_NAME,
+ INTERNAL_INSN_CODE_NAME, ADVANCE_CYCLE_VALUE_NAME);
+
+ fprintf (output_file, " return %s != %s;\n}\n\n",
+ INTERNAL_INSN_CODE_NAME, ADVANCE_CYCLE_VALUE_NAME);
+}
+
/* The function outputs PHR interface functions `dfa_clean_insn_cache'
and 'dfa_clear_single_insn_cache'. */
static void
@@ -9138,6 +9176,7 @@ write_automata (void)
fprintf (output_file, "\n#if %s\n\n", CPU_UNITS_QUERY_MACRO_NAME);
output_get_cpu_unit_code_func ();
output_cpu_unit_reservation_p ();
+ output_insn_has_dfa_reservation_p ();
fprintf (output_file, "\n#endif /* #if %s */\n\n",
CPU_UNITS_QUERY_MACRO_NAME);
output_dfa_clean_insn_cache_func ();
diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c
index d9a8f78..27b040f 100644
--- a/gcc/haifa-sched.c
+++ b/gcc/haifa-sched.c
@@ -1142,6 +1142,9 @@ adjust_priority (rtx prev)
HAIFA_INLINE static void
advance_one_cycle (void)
{
+ if (targetm.sched.dfa_pre_advance_cycle)
+ targetm.sched.dfa_pre_advance_cycle ();
+
if (targetm.sched.dfa_pre_cycle_insn)
state_transition (curr_state,
targetm.sched.dfa_pre_cycle_insn ());
@@ -1151,6 +1154,9 @@ advance_one_cycle (void)
if (targetm.sched.dfa_post_cycle_insn)
state_transition (curr_state,
targetm.sched.dfa_post_cycle_insn ());
+
+ if (targetm.sched.dfa_post_advance_cycle)
+ targetm.sched.dfa_post_advance_cycle ();
}
/* Clock at which the previous instruction was issued. */
diff --git a/gcc/target-def.h b/gcc/target-def.h
index 12b3297..bdaf9f4 100644
--- a/gcc/target-def.h
+++ b/gcc/target-def.h
@@ -310,6 +310,8 @@
#define TARGET_SCHED_DFA_PRE_CYCLE_INSN 0
#define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN 0
#define TARGET_SCHED_DFA_POST_CYCLE_INSN 0
+#define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE 0
+#define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE 0
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 0
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD 0
#define TARGET_SCHED_DFA_NEW_CYCLE 0
@@ -337,7 +339,9 @@
TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN, \
TARGET_SCHED_DFA_PRE_CYCLE_INSN, \
TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN, \
- TARGET_SCHED_DFA_POST_CYCLE_INSN, \
+ TARGET_SCHED_DFA_POST_CYCLE_INSN, \
+ TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE, \
+ TARGET_SCHED_DFA_POST_ADVANCE_CYCLE, \
TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD, \
TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD, \
TARGET_SCHED_DFA_NEW_CYCLE, \
diff --git a/gcc/target.h b/gcc/target.h
index 7094d4d..d1af443 100644
--- a/gcc/target.h
+++ b/gcc/target.h
@@ -303,6 +303,13 @@ struct gcc_target
void (* init_dfa_post_cycle_insn) (void);
rtx (* dfa_post_cycle_insn) (void);
+ /* The values of the following two members are pointers to
+ functions used to simplify the automaton descriptions.
+ dfa_pre_advance_cycle and dfa_post_advance_cycle are getting called
+ immediatelly before and after cycle is advanced. */
+ void (* dfa_pre_advance_cycle) (void);
+ void (* dfa_post_advance_cycle) (void);
+
/* The following member value is a pointer to a function returning value
which defines how many insns in queue `ready' will we try for
multi-pass scheduling. If the member value is nonzero and the
generated by cgit v1.1 at 2025-08-09 08:56:20 +0000