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-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/aarch64/aarch64.md9
-rw-r--r--gcc/testsuite/ChangeLog4
-rw-r--r--gcc/testsuite/gcc.target/aarch64/mvn_zero_ext.c15
4 files changed, 32 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc076c8..6a41975 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2020-05-05 Alex Coplan <alex.coplan@arm.com>
+
+ * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
+
2020-05-05 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94800
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 8c8be3c..ff15505 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4619,6 +4619,15 @@
(set_attr "arch" "*,simd")]
)
+(define_insn "*one_cmpl_zero_extend"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (not:SI (match_operand:SI 1 "register_operand" "r"))))]
+ ""
+ "mvn\\t%w0, %w1"
+ [(set_attr "type" "logic_reg")]
+)
+
(define_insn "*one_cmpl_<optab><mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(not:GPI (SHIFT:GPI (match_operand:GPI 1 "register_operand" "r")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2b48741..e06bcf8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2020-05-05 Alex Coplan <alex.coplan@arm.com>
+
+ * gcc.target/aarch64/mvn_zero_ext.c: New test.
+
2020-05-05 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94800
diff --git a/gcc/testsuite/gcc.target/aarch64/mvn_zero_ext.c b/gcc/testsuite/gcc.target/aarch64/mvn_zero_ext.c
new file mode 100644
index 0000000..3cd2a2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mvn_zero_ext.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/*
+** foo:
+** mvn w0, w0
+** ret
+*/
+unsigned long long
+foo (unsigned a)
+{
+ return ~a;
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */