diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 14 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 6 |
3 files changed, 18 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f9b788c..a3ff07b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2007-01-24 Jakub Jelinek <jakub@redhat.com> + * config/i386/i386.h (x86_cmpxchg16b): Remove const. + (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. + * config/i386/i386.c (x86_cmpxchg16b): Remove const. + (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b + for CPUs that have PTA_CX16 set. + PR middle-end/27416 * gimplify.c (omp_check_private): New function. (gimplify_scan_omp_clauses): Use it for diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9191376..3d1b64d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1018,8 +1018,6 @@ const int x86_use_bt = m_ATHLON_K8; const int x86_cmpxchg = ~m_386; /* Compare and exchange 8 bytes was added for pentium. */ const int x86_cmpxchg8b = ~(m_386 | m_486); -/* Compare and exchange 16 bytes was added for nocona. */ -const int x86_cmpxchg16b = m_NOCONA; /* Exchange and add was added for 80486. */ const int x86_xadd = ~m_386; /* Byteswap was added for 80486. */ @@ -1243,6 +1241,9 @@ enum processor_type ix86_arch; /* true if sse prefetch instruction is not NOOP. */ int x86_prefetch_sse; +/* true if cmpxchg16b is supported. */ +int x86_cmpxchg16b; + /* ix86_regparm_string as a number */ static int ix86_regparm; @@ -1678,7 +1679,8 @@ override_options (void) PTA_3DNOW = 32, PTA_3DNOW_A = 64, PTA_64BIT = 128, - PTA_SSSE3 = 256 + PTA_SSSE3 = 256, + PTA_CX16 = 512 } flags; } const processor_alias_table[] = @@ -1705,10 +1707,10 @@ override_options (void) {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_MMX | PTA_PREFETCH_SSE}, {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT - | PTA_MMX | PTA_PREFETCH_SSE}, + | PTA_MMX | PTA_PREFETCH_SSE | PTA_CX16}, {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT | PTA_MMX - | PTA_PREFETCH_SSE}, + | PTA_PREFETCH_SSE | PTA_CX16}, {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_3DNOW_A}, {"k6", PROCESSOR_K6, PTA_MMX}, @@ -1915,6 +1917,8 @@ override_options (void) target_flags |= MASK_SSSE3; if (processor_alias_table[i].flags & PTA_PREFETCH_SSE) x86_prefetch_sse = true; + if (processor_alias_table[i].flags & PTA_CX16) + x86_cmpxchg16b = true; if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) error ("CPU you selected does not support x86-64 " "instruction set"); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 19dabcc..910f2be 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -199,12 +199,12 @@ extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; extern const int x86_use_ffreep; extern const int x86_inter_unit_moves, x86_schedule; extern const int x86_use_bt; -extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd; +extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd; extern const int x86_use_incdec; extern const int x86_pad_returns; extern const int x86_bswap; extern const int x86_partial_flag_reg_stall; -extern int x86_prefetch_sse; +extern int x86_prefetch_sse, x86_cmpxchg16b; #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) @@ -273,7 +273,7 @@ extern int x86_prefetch_sse; #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) -#define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch)) +#define TARGET_CMPXCHG16B (x86_cmpxchg16b) #define TARGET_XADD (x86_xadd & (1 << ix86_arch)) #define TARGET_BSWAP (x86_bswap & (1 << ix86_arch)) |