diff options
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 18 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 16 |
3 files changed, 18 insertions, 25 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0386102..13d5fe4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2011-10-23 Uros Bizjak <ubizjak@gmail.com> + * config/i386/sse.md (avx2_lshl<mode>3): Remove insn pattern. + (VI248_256): Remove mode iterator. + * config/i386/i386.c (ix86_expand_vec_perm): Use gen_ashlv4di3 + instead of gen_avx2_lshlv4di3. + (bdesc_args): Use CODE_FOR_ashl{v16hi,v8si,v4di}3 instead of + CODE_FOR_avx2_lshl{v16hi,v8si,v4di}3. + +2011-10-23 Uros Bizjak <ubizjak@gmail.com> + * config/i386/sse.md (sseintprefix): Rename from gthrfirstp. (<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Delete expander. (<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>) Merge insn diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index df1a206..ef1bbd3 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19490,9 +19490,9 @@ ix86_expand_vec_perm (rtx operands[]) stands for other 12 bytes. */ /* The bit whether element is from the same lane or the other lane is bit 4, so shift it up by 3 to the MSB position. */ - emit_insn (gen_avx2_lshlv4di3 (gen_lowpart (V4DImode, t1), - gen_lowpart (V4DImode, mask), - GEN_INT (3))); + emit_insn (gen_ashlv4di3 (gen_lowpart (V4DImode, t1), + gen_lowpart (V4DImode, mask), + GEN_INT (3))); /* Clear MSB bits from the mask just in case it had them set. */ emit_insn (gen_avx2_andnotv32qi3 (t2, vt, mask)); /* After this t1 will have MSB set for elements from other lane. */ @@ -26289,12 +26289,12 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI }, { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI }, { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT }, - { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT }, + { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT }, { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT }, { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT }, { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT }, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index dcb2d4b..ee3af03 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -196,7 +196,6 @@ ;; Random 256bit vector integer mode combinations (define_mode_iterator VI124_256 [V32QI V16HI V8SI]) -(define_mode_iterator VI248_256 [V16HI V8SI V4DI]) ;; Int-float size matches (define_mode_iterator VI4F_128 [V4SI V4SF]) @@ -5804,21 +5803,6 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "avx2_lshl<mode>3" - [(set (match_operand:VI248_256 0 "register_operand" "=x") - (ashift:VI248_256 - (match_operand:VI248_256 1 "register_operand" "x") - (match_operand:SI 2 "nonmemory_operand" "xN")))] - "TARGET_AVX2" - "vpsll<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sseishft") - (set_attr "prefix" "vex") - (set (attr "length_immediate") - (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "1") - (const_string "0"))) - (set_attr "mode" "OI")]) - (define_insn "ashl<mode>3" [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x") (ashift:VI248_AVX2 |