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-rw-r--r--gcc/rtl-ssa/insns.cc11
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c21
2 files changed, 29 insertions, 3 deletions
diff --git a/gcc/rtl-ssa/insns.cc b/gcc/rtl-ssa/insns.cc
index 2fa48e0..a54168d 100644
--- a/gcc/rtl-ssa/insns.cc
+++ b/gcc/rtl-ssa/insns.cc
@@ -520,9 +520,14 @@ function_info::record_use (build_info &bi, insn_info *insn,
// the instruction (unusually) references the same register in two
// different but equal-sized modes.
gcc_checking_assert (use->insn () == insn);
- if (HARD_REGISTER_NUM_P (regno)
- && partial_subreg_p (use->mode (), mode))
- use->set_mode (mode);
+ if (HARD_REGISTER_NUM_P (regno))
+ {
+ if (!ordered_p (GET_MODE_PRECISION (use->mode ()),
+ GET_MODE_PRECISION (mode)))
+ use->set_mode (reg_raw_mode[regno]);
+ else if (partial_subreg_p (use->mode (), mode))
+ use->set_mode (mode);
+ }
use->record_reference (ref, false);
}
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
new file mode 100644
index 0000000..bbc02ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
+
+int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
+ safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
+ g_97_l_439;
+void g_97(int * __restrict l_437)
+{
+ for (; g_97_l_439; g_97_l_439 += 1)
+ for (char l_502 = 0; l_502 < 4; l_502++)
+ {
+ int __trans_tmp_14 = ((safe_lshift_func_int32_t_s_s_right >= 2
+ || safe_lshift_func_int32_t_s_s_left)
+ ? 1 : safe_lshift_func_int32_t_s_s_right);
+ long __trans_tmp_15 = __trans_tmp_14 * safe_mul_func_uint64_t_u_u_ui2;
+ unsigned short __trans_tmp_16 = -__trans_tmp_15;
+ int __trans_tmp_7
+ = (__trans_tmp_16 ^ 65535UL) - safe_sub_func_uint64_t_u_u_ui2;
+ *l_437 ^= (short)(__trans_tmp_7 ^ g_79_2);
+ }
+}