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-rw-r--r--gcc/ChangeLog43
-rw-r--r--gcc/config/i386/i386.md6
-rw-r--r--gcc/config/i386/mmx.md29
-rw-r--r--gcc/config/i386/sse.md214
4 files changed, 85 insertions, 207 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2bd5c04..721fe8c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,46 @@
+2008-04-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.md (plogic): New.
+ (plogicprefix): Likewise.
+
+ * config/i386/mmx.md (mmx_<code><mode>3): New.
+ (mmx_and<mode>3): Removed.
+ (mmx_ior<mode>3): Likewise.
+ (mmx_xor<mode>3): Likewise.
+
+ * config/i386/sse.md (<code><mode>3): New.
+ (*<code><mode>3): Likewise.
+ (*<code><mode>3): Likewise.
+ (<code><mode>3): Likewise.
+ (*sse_<code><mode>3): Likewise.
+ (*sse2_<code><mode>3): Likewise.
+ (<code>tf3): Likewise.
+ (*<code>tf3): Likewise.
+ (and<mode>3): Likewise.
+ (*and<mode>3): Likewise.
+ (ior<mode>3): Removed.
+ (*ior<mode>3): Likewise.
+ (xor<mode>3): Likewise.
+ (*xor<mode>3): Likewise.
+ (*and<mode>3): Likewise.
+ (*ior<mode>3): Likewise.
+ (*xor<mode>3): Likewise.
+ (and<mode>3): Likewise.
+ (*sse_and<mode>3): Likewise.
+ (*sse2_and<mode>3): Likewise.
+ (andtf3): Likewise.
+ (*andtf3): Likewise.
+ (ior<mode>3): Likewise.
+ (*sse_ior<mode>3): Likewise.
+ (*sse2_ior<mode>3): Likewise.
+ (iortf3): Likewise.
+ (*iortf3): Likewise.
+ (xor<mode>3): Likewise.
+ (*sse_xor<mode>3): Likewise.
+ (*sse2_xor<mode>3): Likewise.
+ (xortf3): Likewise.
+ (*xortf3): Likewise.
+
2008-04-02 Richard Guenther <rguenther@suse.de>
PR tree-optimization/14495
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a72e772..e2d68bb 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -540,6 +540,12 @@
(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])
+;; Mapping of parallel logic operators
+(define_code_iterator plogic [and ior xor])
+
+;; Base name for insn mnemonic.
+(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
+
;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 63e9025..bfcddc6 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -791,16 +791,6 @@
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "mmx_and<mode>3"
- [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
- (and:MMXMODEI
- (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
(define_insn "mmx_nand<mode>3"
[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
(and:MMXMODEI
@@ -811,27 +801,16 @@
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
-(define_insn "mmx_ior<mode>3"
+(define_insn "mmx_<code><mode>3"
[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
- (ior:MMXMODEI
+ (plogic:MMXMODEI
(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
(match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "por\t{%2, %0|%0, %2}"
+ "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "p<plogicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
-(define_insn "mmx_xor<mode>3"
- [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
- (xor:MMXMODEI
- (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "pxor\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")
- (set_attr "memory" "none")])
-
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral element swizzling
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e1f316b..2b1e7f2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -839,25 +839,6 @@
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_expand "and<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (and:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
-
-(define_insn "*and<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (and:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
- "andp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<MODE>")])
-
(define_insn "<sse>_nand<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(and:SSEMODEF2P
@@ -869,41 +850,22 @@
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
-(define_expand "ior<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (ior:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
-
-(define_insn "*ior<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (ior:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "orp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "xor<mode>3"
+(define_expand "<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (xor:SSEMODEF2P
+ (plogic:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
+ "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*xor<mode>3"
+(define_insn "*<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (xor:SSEMODEF2P
+ (plogic:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "xorp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<plogicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
@@ -912,16 +874,6 @@
;; allocation lossage. These patterns do not allow memory operands
;; because the native instructions read the full 128-bits.
-(define_insn "*and<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (and:MODEF
- (match_operand:MODEF 1 "register_operand" "0")
- (match_operand:MODEF 2 "register_operand" "x")))]
- "SSE_FLOAT_MODE_P (<MODE>mode)"
- "andp<ssemodefsuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<ssevecmode>")])
-
(define_insn "*nand<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(and:MODEF
@@ -933,23 +885,13 @@
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
-(define_insn "*ior<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (ior:MODEF
- (match_operand:MODEF 1 "register_operand" "0")
- (match_operand:MODEF 2 "register_operand" "x")))]
- "SSE_FLOAT_MODE_P (<MODE>mode)"
- "orp<ssemodefsuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<ssevecmode>")])
-
-(define_insn "*xor<mode>3"
+(define_insn "*<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
- (xor:MODEF
+ (plogic:MODEF
(match_operand:MODEF 1 "register_operand" "0")
(match_operand:MODEF 2 "register_operand" "x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "xorp<ssemodefsuffix>\t{%2, %0|%0, %2}"
+ "<plogicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
@@ -3820,35 +3762,6 @@
operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
})
-(define_expand "and<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (and:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
-
-(define_insn "*sse_and<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)
- && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
- "andps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-(define_insn "*sse2_and<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
(define_insn "*sse_nand<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
@@ -3870,24 +3783,6 @@
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
-(define_expand "andtf3"
- [(set (match_operand:TF 0 "register_operand" "")
- (and:TF (match_operand:TF 1 "nonimmediate_operand" "")
- (match_operand:TF 2 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "ix86_fixup_binary_operands_no_copy (AND, TFmode, operands);")
-
-(define_insn "*andtf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
- (and:TF
- (match_operand:TF 1 "nonimmediate_operand" "%0")
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_64BIT && ix86_binary_operator_ok (AND, TFmode, operands)"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
(define_insn "*nandtf3"
[(set (match_operand:TF 0 "register_operand" "=x")
(and:TF
@@ -3899,96 +3794,51 @@
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
-(define_expand "ior<mode>3"
+(define_expand "<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
- (ior:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
+ (plogic:SSEMODEI
+ (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
+ (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE"
- "ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
+ "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*sse_ior<mode>3"
+(define_insn "*sse_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (ior:SSEMODEI
+ (plogic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
- && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "orps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-(define_insn "*sse2_ior<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (ior:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "por\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_expand "iortf3"
- [(set (match_operand:TF 0 "register_operand" "")
- (ior:TF (match_operand:TF 1 "nonimmediate_operand" "")
- (match_operand:TF 2 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "ix86_fixup_binary_operands_no_copy (IOR, TFmode, operands);")
-
-(define_insn "*iortf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
- (ior:TF
- (match_operand:TF 1 "nonimmediate_operand" "%0")
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_64BIT && ix86_binary_operator_ok (IOR, TFmode, operands)"
- "por\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_expand "xor<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
-
-(define_insn "*sse_xor<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (xor:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)
- && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "xorps\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<plogicprefix>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
-(define_insn "*sse2_xor<mode>3"
+(define_insn "*sse2_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (xor:SSEMODEI
+ (plogic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "pxor\t{%2, %0|%0, %2}"
+ "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "p<plogicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
-(define_expand "xortf3"
+(define_expand "<code>tf3"
[(set (match_operand:TF 0 "register_operand" "")
- (xor:TF (match_operand:TF 1 "nonimmediate_operand" "")
- (match_operand:TF 2 "nonimmediate_operand" "")))]
+ (plogic:TF
+ (match_operand:TF 1 "nonimmediate_operand" "")
+ (match_operand:TF 2 "nonimmediate_operand" "")))]
"TARGET_64BIT"
- "ix86_fixup_binary_operands_no_copy (XOR, TFmode, operands);")
+ "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
-(define_insn "*xortf3"
+(define_insn "*<code>tf3"
[(set (match_operand:TF 0 "register_operand" "=x")
- (xor:TF
+ (plogic:TF
(match_operand:TF 1 "nonimmediate_operand" "%0")
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_64BIT && ix86_binary_operator_ok (XOR, TFmode, operands)"
- "pxor\t{%2, %0|%0, %2}"
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+ "p<plogicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
generated by cgit v1.1 at 2025-05-02 05:35:51 +0000