diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 2 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 37 |
3 files changed, 43 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4ebd534..0501612 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Fri Sep 5 16:16:44 1997 Christian Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE> + + * sparc/sparc.md: Add ultrasparc scheduling support. + * sparc/sparc.h (RTX_COSTS): For MULT give v9 a cost of 25 insns. + Fri Sep 5 14:04:59 1997 Philippe De Muyter <phdm@info.ucl.ac.be> * integrate.c (save_for_inline_copying): Use 0, not NULL_PTR, diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index ac86c3a..81b9047 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -2707,7 +2707,7 @@ extern struct rtx_def *legitimize_pic_address (); #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ - return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) \ + return (TARGET_V8 || TARGET_SPARCLITE) \ ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ case DIV: \ case UDIV: \ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 9ac695f..a30749e 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -272,6 +272,43 @@ ;; The multiply unit has a latency of 5. (define_function_unit "tsc701_mul" 1 0 (and (eq_attr "type" "imul") (eq_attr "cpu" "tsc701")) 5 5) + +;; ----- The UltraSPARC-1 scheduling +;; The Ultrasparc can issue 1 - 4 insns per cycle; here we assume +;; four insns/cycle, and hence multiply all costs by four. + +;; Memory delivers its result in three cycles to IU, three cycles to FP +(define_function_unit "memory" 1 0 + (and (eq_attr "type" "load,fpload") (eq_attr "cpu" "ultrasparc")) 12 4) +(define_function_unit "memory" 1 0 + (and (eq_attr "type" "store,fpstore") (eq_attr "cpu" "ultrasparc")) 4 4) +(define_function_unit "ieu" 1 0 + (and (eq_attr "type" "ialu") (eq_attr "cpu" "ultrasparc")) 1 2) +(define_function_unit "ieu" 1 0 + (and (eq_attr "type" "shift") (eq_attr "cpu" "ultrasparc")) 1 4) +(define_function_unit "ieu" 1 0 + (and (eq_attr "type" "cmove") (eq_attr "cpu" "ultrasparc")) 8 4) + +;; Timings; throughput/latency +;; ?? FADD 1/3 add/sub, format conv, compar, abs, neg +;; ?? FMUL 1/3 +;; ?? FDIVs 1/12 +;; ?? FDIVd 1/22 +;; ?? FSQRTs 1/12 +;; ?? FSQRTd 1/22 + +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fp") (eq_attr "cpu" "ultrasparc")) 12 2) +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpcmp") (eq_attr "cpu" "ultrasparc")) 8 2) +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpmul") (eq_attr "cpu" "ultrasparc")) 12 2) +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpdivs") (eq_attr "cpu" "ultrasparc")) 48 2) +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpdivd") (eq_attr "cpu" "ultrasparc")) 88 2) +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpsqrt") (eq_attr "cpu" "ultrasparc")) 48 2) ;; Compare instructions. ;; This controls RTL generation and register allocation. |