aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--gcc/ChangeLog20
-rw-r--r--gcc/config/sh/sh-protos.h3
-rw-r--r--gcc/config/sh/sh.c50
-rw-r--r--gcc/config/sh/sh.h3
-rw-r--r--gcc/config/sh/sh.md182
5 files changed, 122 insertions, 136 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 00355f4..f4a90da 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+Tue Oct 31 15:33:27 2000 J"orn Rennecke <amylaar@redhat.com>
+
+ * sh-protos.h (reg_no_subreg_operand, emit_fpscr_use): Don't declare.
+ (fp_extended_operand, emit_fpscr_use): Likewise.
+ * sh.c (reg_no_subreg_operand, fp_extended_operand): Delete functions.
+ (fpul_operand): New function.
+ * sh.h (PREDICATE_CODES): Remove reg_no_subreg_operand and
+ fp_extended_operand. Add fpul_operand.
+ * sh.md (mulsf3, mulsf3_i4): Use fp_arith_reg_operand for "f" operands.
+ (mulsf3_ie, macsf3, cmpgtsf_t, cmpeqsf_t, ieee_ccmpeqsf_t): Likewise.
+ (cmpgtsf_t_i4, cmpeqsf_t_i4, ieee_ccmpeqsf_t_4, negsf2): Likewise.
+ (negsf2_i, sqrtsf2, sqrtsf2_i, abssf2, abssf2_i, adddf3): Likewise.
+ (adddf3_i, subdf3, subdf3_i, muldf3, muldf3_i, divdf3): Likewise.
+ (divdf3_i): Likewise.
+ (floatsisf2): Likewise. Use fpul_operand for 'y' operand.
+ (floatsisf2_i4, floatsisf2_ie, fix_truncsfsi2): Likewise.
+ (fix_truncsfsi2_i4, fixsfsi, floatsidf2, floatsidf2_i): Likewise.
+ (fix_truncdfsi2, fix_truncdfsi2_i, extendsfdf2): Likewise.
+ (extendsfdf2_i4, truncdfsf2, truncdfsf2_i4): Likewise.
+
2000-10-31 Bernd Schmidt <bernds@redhat.co.uk>
* config/i386/i386.c (ix86_init_builtins): Correct return type
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index e643d08..21872ac 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -81,9 +81,7 @@ extern int system_reg_operand PARAMS ((rtx, enum machine_mode));
extern int general_movsrc_operand PARAMS ((rtx, enum machine_mode));
extern int general_movdst_operand PARAMS ((rtx, enum machine_mode));
extern int arith_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_no_subreg_operand PARAMS ((rtx, enum machine_mode));
extern int fp_arith_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int fp_extended_operand PARAMS ((rtx, enum machine_mode));
extern int arith_operand PARAMS ((rtx, enum machine_mode));
extern int arith_reg_or_0_operand PARAMS ((rtx, enum machine_mode));
extern int logical_operand PARAMS ((rtx, enum machine_mode));
@@ -120,7 +118,6 @@ extern void sh_expand_epilogue PARAMS ((void));
extern int sh_need_epilogue PARAMS ((void));
extern void function_epilogue PARAMS ((FILE *, int));
extern int initial_elimination_offset PARAMS ((int, int));
-extern void emit_fpscr_use PARAMS ((void));
extern int fldi_ok PARAMS ((void));
#ifdef HARD_CONST
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 5c7c81c..74d365b 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -4659,20 +4659,6 @@ general_movdst_operand (op, mode)
return general_operand (op, mode);
}
-/* Accept a register, but not a subreg of any kind. This allows us to
- avoid pathological cases in reload wrt data movement common in
- int->fp conversion. */
-
-int
-reg_no_subreg_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == SUBREG)
- return 0;
- return register_operand (op, mode);
-}
-
/* Returns 1 if OP is a normal arithmetic register. */
int
@@ -4720,33 +4706,6 @@ fp_arith_reg_operand (op, mode)
return 0;
}
-int
-fp_extended_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == FLOAT_EXTEND && GET_MODE (op) == mode)
- {
- op = XEXP (op, 0);
- mode = GET_MODE (op);
- }
- if (register_operand (op, mode))
- {
- int regno;
-
- if (GET_CODE (op) == REG)
- regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
- regno = REGNO (SUBREG_REG (op));
- else
- return 1;
-
- return (regno != T_REG && regno != PR_REG && regno > 15
- && regno != MACH_REG && regno != MACL_REG);
- }
- return 0;
-}
-
/* Returns 1 if OP is a valid source operand for an arithmetic insn. */
int
@@ -4857,6 +4816,15 @@ fpscr_operand (op, mode)
}
int
+fpul_operand (op, mode)
+ rtx op;
+{
+ return (GET_CODE (op) == REG
+ && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
+ && GET_MODE (op) == mode);
+}
+
+int
commutative_float_operator (op, mode)
rtx op;
enum machine_mode mode;
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index a73ebad..d217f35 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -2231,13 +2231,12 @@ extern struct rtx_def *fpscr_rtx;
#define PREDICATE_CODES \
{"arith_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_reg_operand", {SUBREG, REG}}, \
- {"reg_no_subreg_operand", {REG}}, \
{"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{"binary_float_operator", {PLUS, MULT}}, \
{"commutative_float_operator", {PLUS, MULT}}, \
{"fp_arith_reg_operand", {SUBREG, REG}}, \
- {"fp_extended_operand", {SUBREG, REG, FLOAT_EXTEND}}, \
{"fpscr_operand", {REG}}, \
+ {"fpul_operand", {REG}}, \
{"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
{"general_movdst_operand", {SUBREG, REG, MEM}}, \
{"logical_operand", {SUBREG, REG, CONST_INT}}, \
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 4031d86..4021fb2 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -4163,9 +4163,9 @@
;; SH3E, we use a separate insn for SH3E mulsf3.
(define_expand "mulsf3"
- [(match_operand:SF 0 "arith_reg_operand" "")
- (match_operand:SF 1 "arith_reg_operand" "")
- (match_operand:SF 2 "arith_reg_operand" "")]
+ [(match_operand:SF 0 "fp_arith_reg_operand" "")
+ (match_operand:SF 1 "fp_arith_reg_operand" "")
+ (match_operand:SF 2 "fp_arith_reg_operand" "")]
"TARGET_SH3E"
"
{
@@ -4177,9 +4177,9 @@
}")
(define_insn "mulsf3_i4"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
- (match_operand:SF 2 "arith_reg_operand" "f")))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
+ (match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
"TARGET_SH3E"
"fmul %2,%0"
@@ -4187,17 +4187,17 @@
(set_attr "fp_mode" "single")])
(define_insn "mulsf3_ie"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
- (match_operand:SF 2 "arith_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
+ (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SH3E && ! TARGET_SH4"
"fmul %2,%0"
[(set_attr "type" "fp")])
(define_insn "*macsf3"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
- (match_operand:SF 2 "arith_reg_operand" "f"))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
+ (match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "arith_reg_operand" "0")))
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
"TARGET_SH3E && ! TARGET_SH4"
@@ -4223,8 +4223,8 @@
(set_attr "fp_mode" "single")])
(define_expand "floatsisf2"
- [(set (match_operand:SF 0 "arith_reg_operand" "")
- (float:SF (match_operand:SI 1 "reg_no_subreg_operand" "")))]
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
+ (float:SF (match_operand:SI 1 "fpul_operand" "")))]
"TARGET_SH3E"
"
{
@@ -4236,8 +4236,8 @@
}")
(define_insn "floatsisf2_i4"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (float:SF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (float:SF (match_operand:SI 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"float %1,%0"
@@ -4245,15 +4245,15 @@
(set_attr "fp_mode" "single")])
(define_insn "*floatsisf2_ie"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (float:SF (match_operand:SI 1 "reg_no_subreg_operand" "y")))]
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
"TARGET_SH3E && ! TARGET_SH4"
"float %1,%0"
[(set_attr "type" "fp")])
(define_expand "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=y")
- (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
+ [(set (match_operand:SI 0 "fpul_operand" "=y")
+ (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SH3E"
"
{
@@ -4265,8 +4265,8 @@
}")
(define_insn "fix_truncsfsi2_i4"
- [(set (match_operand:SI 0 "register_operand" "=y")
- (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
+ [(set (match_operand:SI 0 "fpul_operand" "=y")
+ (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"ftrc %1,%0"
@@ -4296,40 +4296,41 @@
;; (set (match_dup 0) (reg:SI 22))])
(define_insn "*fixsfsi"
- [(set (match_operand:SI 0 "register_operand" "=y")
- (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
+ [(set (match_operand:SI 0 "fpul_operand" "=y")
+ (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SH3E && ! TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "fp")])
(define_insn "cmpgtsf_t"
- [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f")))]
+ [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SH3E && ! TARGET_SH4"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(define_insn "cmpeqsf_t"
- [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f")))]
+ [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SH3E && ! TARGET_SH4"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(define_insn "ieee_ccmpeqsf_t"
- [(set (reg:SI 18) (ior:SI (reg:SI 18)
- (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f"))))]
+ [(set (reg:SI 18)
+ (ior:SI (reg:SI 18)
+ (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
"TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
(define_insn "cmpgtsf_t_i4"
- [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f")))
+ [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"fcmp/gt %1,%0"
@@ -4337,8 +4338,8 @@
(set_attr "fp_mode" "single")])
(define_insn "cmpeqsf_t_i4"
- [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f")))
+ [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"fcmp/eq %1,%0"
@@ -4346,9 +4347,10 @@
(set_attr "fp_mode" "single")])
(define_insn "*ieee_ccmpeqsf_t_4"
- [(set (reg:SI 18) (ior:SI (reg:SI 18)
- (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
- (match_operand:SF 1 "arith_reg_operand" "f"))))
+ [(set (reg:SI 18)
+ (ior:SI (reg:SI 18)
+ (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+ (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_IEEE && TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
@@ -4367,14 +4369,14 @@
}")
(define_expand "negsf2"
- [(match_operand:SF 0 "arith_reg_operand" "")
- (match_operand:SF 1 "arith_reg_operand" "")]
+ [(match_operand:SF 0 "fp_arith_reg_operand" "")
+ (match_operand:SF 1 "fp_arith_reg_operand" "")]
"TARGET_SH3E"
"{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
(define_insn "negsf2_i"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH3E"
"fneg %0"
@@ -4382,14 +4384,14 @@
(set_attr "fp_mode" "single")])
(define_expand "sqrtsf2"
- [(match_operand:SF 0 "arith_reg_operand" "")
- (match_operand:SF 1 "arith_reg_operand" "")]
+ [(match_operand:SF 0 "fp_arith_reg_operand" "")
+ (match_operand:SF 1 "fp_arith_reg_operand" "")]
"TARGET_SH3E"
"{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
(define_insn "sqrtsf2_i"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "arith_reg_operand" "0")))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH3E"
"fsqrt %0"
@@ -4397,14 +4399,14 @@
(set_attr "fp_mode" "single")])
(define_expand "abssf2"
- [(match_operand:SF 0 "arith_reg_operand" "")
- (match_operand:SF 1 "arith_reg_operand" "")]
+ [(match_operand:SF 0 "fp_arith_reg_operand" "")
+ (match_operand:SF 1 "fp_arith_reg_operand" "")]
"TARGET_SH3E"
"{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
(define_insn "abssf2_i"
- [(set (match_operand:SF 0 "arith_reg_operand" "=f")
- (abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH3E"
"fabs %0"
@@ -4412,16 +4414,16 @@
(set_attr "fp_mode" "single")])
(define_expand "adddf3"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:DF 1 "arith_reg_operand" "")
- (match_operand:DF 2 "arith_reg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")
+ (match_operand:DF 2 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
(define_insn "adddf3_i"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (plus:DF (match_operand:DF 1 "arith_reg_operand" "%0")
- (match_operand:DF 2 "arith_reg_operand" "f")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
+ (match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
"TARGET_SH4"
"fadd %2,%0"
@@ -4429,16 +4431,16 @@
(set_attr "fp_mode" "double")])
(define_expand "subdf3"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:DF 1 "arith_reg_operand" "")
- (match_operand:DF 2 "arith_reg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")
+ (match_operand:DF 2 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
(define_insn "subdf3_i"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (minus:DF (match_operand:DF 1 "arith_reg_operand" "0")
- (match_operand:DF 2 "arith_reg_operand" "f")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
+ (match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
"TARGET_SH4"
"fsub %2,%0"
@@ -4446,16 +4448,16 @@
(set_attr "fp_mode" "double")])
(define_expand "muldf3"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:DF 1 "arith_reg_operand" "")
- (match_operand:DF 2 "arith_reg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")
+ (match_operand:DF 2 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
(define_insn "muldf3_i"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (mult:DF (match_operand:DF 1 "arith_reg_operand" "%0")
- (match_operand:DF 2 "arith_reg_operand" "f")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
+ (match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
"TARGET_SH4"
"fmul %2,%0"
@@ -4463,16 +4465,16 @@
(set_attr "fp_mode" "double")])
(define_expand "divdf3"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:DF 1 "arith_reg_operand" "")
- (match_operand:DF 2 "arith_reg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")
+ (match_operand:DF 2 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
(define_insn "divdf3_i"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (div:DF (match_operand:DF 1 "arith_reg_operand" "0")
- (match_operand:DF 2 "arith_reg_operand" "f")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
+ (match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
"TARGET_SH4"
"fdiv %2,%0"
@@ -4480,8 +4482,8 @@
(set_attr "fp_mode" "double")])
(define_expand "floatsidf2"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:SI 1 "reg_no_subreg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:SI 1 "fpul_operand" "")]
"TARGET_SH4"
"
{
@@ -4490,8 +4492,8 @@
}")
(define_insn "floatsidf2_i"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (float:DF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (float:DF (match_operand:SI 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"float %1,%0"
@@ -4499,8 +4501,8 @@
(set_attr "fp_mode" "double")])
(define_expand "fix_truncdfsi2"
- [(match_operand:SI 0 "arith_reg_operand" "=r")
- (match_operand:DF 1 "arith_reg_operand" "f")]
+ [(match_operand:SI 0 "fpul_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"
{
@@ -4509,8 +4511,8 @@
}")
(define_insn "fix_truncdfsi2_i"
- [(set (match_operand:SI 0 "register_operand" "=y")
- (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
+ [(set (match_operand:SI 0 "fpul_operand" "=y")
+ (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"ftrc %1,%0"
@@ -4624,8 +4626,8 @@
(set_attr "fp_mode" "double")])
(define_expand "extendsfdf2"
- [(match_operand:DF 0 "arith_reg_operand" "")
- (match_operand:SF 1 "reg_no_subreg_operand" "")]
+ [(match_operand:DF 0 "fp_arith_reg_operand" "")
+ (match_operand:SF 1 "fpul_operand" "")]
"TARGET_SH4"
"
{
@@ -4634,8 +4636,8 @@
}")
(define_insn "extendsfdf2_i4"
- [(set (match_operand:DF 0 "arith_reg_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "reg_no_subreg_operand" "y")))
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
+ (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"fcnvsd %1,%0"
@@ -4643,8 +4645,8 @@
(set_attr "fp_mode" "double")])
(define_expand "truncdfsf2"
- [(match_operand:SF 0 "arith_reg_operand" "")
- (match_operand:DF 1 "arith_reg_operand" "")]
+ [(match_operand:SF 0 "fpul_operand" "")
+ (match_operand:DF 1 "fp_arith_reg_operand" "")]
"TARGET_SH4"
"
{
@@ -4653,8 +4655,8 @@
}")
(define_insn "truncdfsf2_i4"
- [(set (match_operand:SF 0 "register_operand" "=y")
- (float_truncate:SF (match_operand:DF 1 "arith_reg_operand" "f")))
+ [(set (match_operand:SF 0 "fpul_operand" "=y")
+ (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"fcnvds %1,%0"
generated by cgit v1.1 at 2025-06-05 19:46:19 +0000