diff options
| -rw-r--r-- | gcc/config/i386/i386-expand.cc | 4 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 46 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr88873.c | 11 |
3 files changed, 49 insertions, 12 deletions
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index a82c2bd..a5c000f 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -558,7 +558,7 @@ ix86_expand_move (machine_mode mode, rtx operands[]) op0 = SUBREG_REG (op0); tmp = gen_rtx_AND (TImode, copy_rtx (op0), tmp); if (mode == DFmode) - op1 = force_reg (DImode, gen_lowpart (DImode, op1)); + op1 = gen_lowpart (DImode, op1); op1 = gen_rtx_ZERO_EXTEND (TImode, op1); op1 = gen_rtx_IOR (TImode, tmp, op1); } @@ -570,7 +570,7 @@ ix86_expand_move (machine_mode mode, rtx operands[]) op0 = SUBREG_REG (op0); tmp = gen_rtx_AND (TImode, copy_rtx (op0), tmp); if (mode == DFmode) - op1 = force_reg (DImode, gen_lowpart (DImode, op1)); + op1 = gen_lowpart (DImode, op1); op1 = gen_rtx_ZERO_EXTEND (TImode, op1); op1 = gen_rtx_ASHIFT (TImode, op1, GEN_INT (64)); op1 = gen_rtx_IOR (TImode, tmp, op1); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 47ea050..8c54aa5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12408,21 +12408,47 @@ DONE; }) -(define_insn_and_split "*concat<mode><dwi>3_3" - [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,r,&r") - (any_or_plus:<DWI> - (ashift:<DWI> - (zero_extend:<DWI> - (match_operand:DWIH 1 "nonimmediate_operand" "r,m,r,m")) +(define_insn_and_split "*concatditi3_3" + [(set (match_operand:TI 0 "nonimmediate_operand" "=ro,r,r,&r,x") + (any_or_plus:TI + (ashift:TI + (zero_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "r,m,r,m,x")) (match_operand:QI 2 "const_int_operand")) - (zero_extend:<DWI> - (match_operand:DWIH 3 "nonimmediate_operand" "r,r,m,m"))))] - "INTVAL (operands[2]) == <MODE_SIZE> * BITS_PER_UNIT" + (zero_extend:TI + (match_operand:DI 3 "nonimmediate_operand" "r,r,m,m,0"))))] + "TARGET_64BIT + && INTVAL (operands[2]) == 64" + "#" + "&& reload_completed" + [(const_int 0)] +{ + if (SSE_REG_P (operands[0])) + { + rtx tmp = gen_rtx_REG (V2DImode, REGNO (operands[0])); + emit_insn (gen_vec_concatv2di (tmp, operands[3], operands[1])); + } + else + split_double_concat (TImode, operands[0], operands[3], operands[1]); + DONE; +}) + +(define_insn_and_split "*concatsidi3_3" + [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,r,r,&r") + (any_or_plus:DI + (ashift:DI + (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "r,m,r,m")) + (match_operand:QI 2 "const_int_operand")) + (zero_extend:DI + (match_operand:SI 3 "nonimmediate_operand" "r,r,m,m"))))] + "!TARGET_64BIT + && INTVAL (operands[2]) == 32" "#" "&& reload_completed" [(const_int 0)] { - split_double_concat (<DWI>mode, operands[0], operands[3], operands[1]); + split_double_concat (DImode, operands[0], operands[3], operands[1]); DONE; }) diff --git a/gcc/testsuite/gcc.target/i386/pr88873.c b/gcc/testsuite/gcc.target/i386/pr88873.c new file mode 100644 index 0000000..d893aac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr88873.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=cascadelake" } */ + +typedef struct { double x, y; } s_t; + +s_t foo (s_t a, s_t b, s_t c) +{ + return (s_t) { __builtin_fma(a.x, b.x, c.x), __builtin_fma (a.y, b.y, c.y) }; +} + +/* { dg-final { scan-assembler-times "vpunpcklqdq" 3 } } */ |