diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 10 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fix_extend1.c | 17 |
3 files changed, 33 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 370344c..956fbde 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-05-31 Michael Collison <michael.collison@arm.com> + + * config/aarch64/aarch64.md: + (*fix_to_zero_extenddfdi2): New pattern. + * gcc.target/aarch64/fix_extend1.c: New testcase. + 2018-05-31 Qing Zhao <qing.zhao@oracle.com> PR middle-end/78809 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7a0e34d..2539f2e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5103,6 +5103,16 @@ [(set_attr "type" "f_cvtf2i")] ) +(define_insn "*fix_to_zero_extend<mode>di2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unsigned_fix:SI + (match_operand:GPF 1 "register_operand" "w"))))] + "TARGET_FLOAT" + "fcvtzu\t%w0, %<s>1" + [(set_attr "type" "f_cvtf2i")] +) + (define_insn "<optab><fcvt_target><GPF:mode>2" [(set (match_operand:GPF 0 "register_operand" "=w,w") (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/fix_extend1.c b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c new file mode 100644 index 0000000..3a251d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long +f7 (double x) +{ + return (unsigned) x; +} + +unsigned long +f7_2 (float x) +{ + return (unsigned) x; +} + +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, d\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */ |