diff options
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 32 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a308204..d603091 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-02-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR rtl-optimization/68664 + * config/aarch64/aarch64.c (aarch64_sched_can_speculate_insn): + New function. + (TARGET_SCHED_CAN_SPECULATE_INSN): Define. + 2017-02-14 Amit Pawar <amit.pawar@amd.com> * config/i386/i386.c (znver1_cost): Fix the alignment for function and diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4be3131..4540406 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -14682,6 +14682,35 @@ aarch64_excess_precision (enum excess_precision_type type) return FLT_EVAL_METHOD_UNPREDICTABLE; } +/* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be + scheduled for speculative execution. Reject the long-running division + and square-root instructions. */ + +static bool +aarch64_sched_can_speculate_insn (rtx_insn *insn) +{ + switch (get_attr_type (insn)) + { + case TYPE_SDIV: + case TYPE_UDIV: + case TYPE_FDIVS: + case TYPE_FDIVD: + case TYPE_FSQRTS: + case TYPE_FSQRTD: + case TYPE_NEON_FP_SQRT_S: + case TYPE_NEON_FP_SQRT_D: + case TYPE_NEON_FP_SQRT_S_Q: + case TYPE_NEON_FP_SQRT_D_Q: + case TYPE_NEON_FP_DIV_S: + case TYPE_NEON_FP_DIV_D: + case TYPE_NEON_FP_DIV_S_Q: + case TYPE_NEON_FP_DIV_D_Q: + return false; + default: + return true; + } +} + /* Target-specific selftests. */ #if CHECKING_P @@ -15070,6 +15099,9 @@ aarch64_libgcc_floating_mode_supported_p #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ aarch64_use_by_pieces_infrastructure_p +#undef TARGET_SCHED_CAN_SPECULATE_INSN +#define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn + #undef TARGET_CAN_USE_DOLOOP_P #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost |