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| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 7 |
2 files changed, 12 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1c5617..adaec48 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-02-01 Richard Sandiford <richard.sandiford@linaro.org> + + PR tearget/83845 + * config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten + check for operands that need to go through aarch64_sve_reload_be. + 2018-02-01 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/81661 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 174310c..656dd76 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7249,9 +7249,14 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, machine_mode mode, secondary_reload_info *sri) { + /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled + directly by the *aarch64_sve_mov<mode>_be move pattern. See the + comment at the head of aarch64-sve.md for more details about the + big-endian handling. */ if (BYTES_BIG_ENDIAN && reg_class_subset_p (rclass, FP_REGS) - && (MEM_P (x) || (REG_P (x) && !HARD_REGISTER_P (x))) + && !((REG_P (x) && HARD_REGISTER_P (x)) + || aarch64_simd_valid_immediate (x, NULL)) && aarch64_sve_data_mode_p (mode)) { sri->icode = CODE_FOR_aarch64_sve_reload_be; |