diff options
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 40 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/wmul-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/wmul-3.c | 18 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/wmul-4.c | 18 |
6 files changed, 79 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 38fd8a4..059542a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2010-06-29 Bernd Schmidt <bernds@codesourcery.com> + + PR target/43902 + * config/arm/arm.md (maddsidi4, umaddsidi4): New expanders. + (maddhisi4): Renamed from mulhisi3addsi. Operands renumbered. + (maddhidi4): Likewise. + 2010-06-29 Nathan Froyd <froydnj@codesourcery.com> * calls.c, dse.c, expr.c, function.c: Call targetm.calls.function_arg, diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1608929..725d505 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1422,7 +1422,15 @@ (set_attr "predicable" "yes")] ) -;; Unnamed template to match long long multiply-accumulate (smlal) +(define_expand "maddsidi4" + [(set (match_operand:DI 0 "s_register_operand" "") + (plus:DI + (mult:DI + (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) + (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) + (match_operand:DI 3 "s_register_operand" "")))] + "TARGET_32BIT && arm_arch3m" + "") (define_insn "*mulsidi3adddi" [(set (match_operand:DI 0 "s_register_operand" "=&r") @@ -1518,7 +1526,15 @@ (set_attr "predicable" "yes")] ) -;; Unnamed template to match long long unsigned multiply-accumulate (umlal) +(define_expand "umaddsidi4" + [(set (match_operand:DI 0 "s_register_operand" "") + (plus:DI + (mult:DI + (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) + (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) + (match_operand:DI 3 "s_register_operand" "")))] + "TARGET_32BIT && arm_arch3m" + "") (define_insn "*umulsidi3adddi" [(set (match_operand:DI 0 "s_register_operand" "=&r") @@ -1686,29 +1702,29 @@ (set_attr "predicable" "yes")] ) -(define_insn "*mulhisi3addsi" +(define_insn "maddhisi4" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (match_operand:SI 1 "s_register_operand" "r") + (plus:SI (match_operand:SI 3 "s_register_operand" "r") (mult:SI (sign_extend:SI - (match_operand:HI 2 "s_register_operand" "%r")) + (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:SI - (match_operand:HI 3 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r")))))] "TARGET_DSP_MULTIPLY" - "smlabb%?\\t%0, %2, %3, %1" + "smlabb%?\\t%0, %1, %2, %3" [(set_attr "insn" "smlaxy") (set_attr "predicable" "yes")] ) -(define_insn "*mulhidi3adddi" +(define_insn "*maddhidi4" [(set (match_operand:DI 0 "s_register_operand" "=r") (plus:DI - (match_operand:DI 1 "s_register_operand" "0") + (match_operand:DI 3 "s_register_operand" "0") (mult:DI (sign_extend:DI - (match_operand:HI 2 "s_register_operand" "%r")) + (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:DI - (match_operand:HI 3 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r")))))] "TARGET_DSP_MULTIPLY" - "smlalbb%?\\t%Q0, %R0, %2, %3" + "smlalbb%?\\t%Q0, %R0, %1, %2" [(set_attr "insn" "smlalxy") (set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 958ddef..7338354 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2010-06-29 Bernd Schmidt <bernds@codesourcery.com> + + PR target/43902 + * gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb. + * gcc.target/arm/wmul-3.c: New test. + * gcc.target/arm/wmul-4.c: New test. + 2010-06-29 H.J. Lu <hongjiu.lu@intel.com> PR rtl-optimization/44659 diff --git a/gcc/testsuite/gcc.target/arm/wmul-1.c b/gcc/testsuite/gcc.target/arm/wmul-1.c index df85e7c..ccb3041 100644 --- a/gcc/testsuite/gcc.target/arm/wmul-1.c +++ b/gcc/testsuite/gcc.target/arm/wmul-1.c @@ -15,4 +15,4 @@ int mac(const short *a, const short *b, int sqr, int *sum) return sqr; } -/* { dg-final { scan-assembler-times "smulbb" 2 } } */ +/* { dg-final { scan-assembler-times "smlabb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-3.c b/gcc/testsuite/gcc.target/arm/wmul-3.c new file mode 100644 index 0000000..325dceb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv6t2" } */ + +int mac(const short *a, const short *b, int sqr, int *sum) +{ + int i; + int dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp -= b[i] * a[i]; + sqr -= b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "smulbb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-4.c b/gcc/testsuite/gcc.target/arm/wmul-4.c new file mode 100644 index 0000000..e8642f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv6t2" } */ + +int mac(const int *a, const int *b, long long sqr, long long *sum) +{ + int i; + long long dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp += (long long) b[i] * a[i]; + sqr += (long long) b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "smlal" 2 } } */ |