diff options
| -rw-r--r-- | gcc/ChangeLog | 15 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 13 |
2 files changed, 23 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2dee412..2098bae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -7,6 +7,21 @@ Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/sse.md + (define_mode_iterator VF1_AVX512VL): New. + (define_insn "ufloatv16siv16sf2<mask_name><round_name>"): Delete. + (define_insn "ufloat<sseintvecmodelower><mode>2<mask_name><round_name>"): + New. + +2014-08-18 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/i386.c: Rename ufloatv8siv8df_mask to ufloatv8siv8df2_mask. * config/i386/i386.md (define_code_iterator any_float): New. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4dd2af9..cc0f06a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -237,6 +237,9 @@ (define_mode_iterator VF2_AVX512VL [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) +(define_mode_iterator VF1_AVX512VL + [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")]) + ;; All vector integer modes (define_mode_iterator VI [(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") @@ -3686,15 +3689,15 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "ufloatv16siv16sf2<mask_name><round_name>" - [(set (match_operand:V16SF 0 "register_operand" "=v") - (unsigned_float:V16SF - (match_operand:V16SI 1 "<round_nimm_predicate>" "<round_constraint>")))] +(define_insn "ufloat<sseintvecmodelower><mode>2<mask_name><round_name>" + [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v") + (unsigned_float:VF1_AVX512VL + (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] "TARGET_AVX512F" "vcvtudq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") - (set_attr "mode" "V16SF")]) + (set_attr "mode" "<MODE>")]) (define_expand "floatuns<sseintvecmodelower><mode>2" [(match_operand:VF1 0 "register_operand") |