diff options
4 files changed, 92 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c new file mode 100644 index 0000000..2b87321 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vint16m1_t +#define T int16_t +#define ELEM_SIZE 16 +#define SUFFIX i16 +#define FUNC __riscv_vaadd_vv_i16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c new file mode 100644 index 0000000..b95699b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vint32m1_t +#define T int32_t +#define ELEM_SIZE 32 +#define SUFFIX i32 +#define FUNC __riscv_vaadd_vv_i32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c new file mode 100644 index 0000000..48b6010 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vint64m1_t +#define T int64_t +#define ELEM_SIZE 64 +#define SUFFIX i64 +#define FUNC __riscv_vaadd_vv_i64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c new file mode 100644 index 0000000..d07a625 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vint8m1_t +#define T int8_t +#define ELEM_SIZE 8 +#define SUFFIX i8 +#define FUNC __riscv_vaadd_vv_i8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ |