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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2015-06-12 09:49:41 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2015-06-12 09:49:41 +0000 |
| commit | 57e6d9be77b9865aa27ed97d90d700969062108b (patch) | |
| tree | d887583d8ab96846a95ce8ef8d868305bb6c9962 /libstdc++-v3/config | |
| parent | 40ad260d6c729000531186ed0ae7f572f11052b6 (diff) | |
| download | gcc-57e6d9be77b9865aa27ed97d90d700969062108b.zip gcc-57e6d9be77b9865aa27ed97d90d700969062108b.tar.gz gcc-57e6d9be77b9865aa27ed97d90d700969062108b.tar.bz2 | |
Use atomics in guard.cc.
This provides proper definitions for _GLIBCXX_READ_MEM_BARRIER and
_GLIBCXX_WRITE_MEM_BARRIER, rewrites the guards in terms of proper
atomic extensions and removes internal uses of
_GLIBCXX_READ_MEM_BARRIER and _GLIBCXX_WRITE_MEM_BARRIER and replaces
them with equivalent atomics.
2015-06-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/66200
PR c++/66192
* * config/cpu/generic/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER): Define
(_GLIBCXX_WRITE_MEM_BARRIER): Likewise
* include/bits/shared_ptr_base.h: Use ACQ_REL barrier.
* include/ext/atomicity.h: Likewise.
* include/tr1/shared_ptr.h: Likewise.
* libsupc++/guard.cc (__test_and_acquire): Rewrite with atomics.
Update comment.
(__set_and_release): Likewise.
* testsuite/20_util/shared_ptr/cons/43820_neg.cc (test01): Adjust for
line numbers.
* testsuite/20_util/shared_ptr/cons/void_neg.cc: Likewise.
* testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc:
Likewise.
From-SVN: r224411
Diffstat (limited to 'libstdc++-v3/config')
| -rw-r--r-- | libstdc++-v3/config/cpu/generic/atomic_word.h | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/libstdc++-v3/config/cpu/generic/atomic_word.h b/libstdc++-v3/config/cpu/generic/atomic_word.h index 19038bb..ccf1e5a 100644 --- a/libstdc++-v3/config/cpu/generic/atomic_word.h +++ b/libstdc++-v3/config/cpu/generic/atomic_word.h @@ -31,17 +31,10 @@ typedef int _Atomic_word; -// Define these two macros using the appropriate memory barrier for the target. -// The commented out versions below are the defaults. -// See ia64/atomic_word.h for an alternative approach. - -// This one prevents loads from being hoisted across the barrier; -// in other words, this is a Load-Load acquire barrier. -// This is necessary iff TARGET_RELAXED_ORDERING is defined in tm.h. -// #define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("":::"memory") - -// This one prevents stores from being sunk across the barrier; in other -// words, a Store-Store release barrier. -// #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("":::"memory") + +// This is a memory order acquire fence. +#define _GLIBCXX_READ_MEM_BARRIER __atomic_thread_fence (__ATOMIC_ACQUIRE) +// This is a memory order release fence. +#define _GLIBCXX_WRITE_MEM_BARRIER __atomic_thread_fence (__ATOMIC_RELEASE) #endif |