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authorRichard Sandiford <richard.sandiford@arm.com>2019-08-14 08:21:01 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2019-08-14 08:21:01 +0000
commit0254ed7970e64abd82f21aedf9373720a73671c7 (patch)
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parentc9c5a8090c58b84c1eb45e39e77eee223f992009 (diff)
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[AArch64] Commonise some SVE FP patterns
This patch uses a single expander for generic FP binary optabs that map to predicated SVE instructions. This makes them consistent with the associated conditional optabs, which already work this way. The patch also generalises the division handling to be one example of a register-only predicated FP operation. The ACLE patches will add FMULX to the same category. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org> gcc/ * config/aarch64/iterators.md (SVE_COND_FP_BINARY_REG): New int iterator. (sve_pred_fp_rhs1_operand, sve_pred_fp_rhs1_operand): New int attributes. * config/aarch64/aarch64-sve.md (add<SVE_F:mode>3, sub<SVE_F:mode>3) (mul<SVE_F:mode>3, div<SVE_F:mode>3) (<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Merge into... (<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this new expander. (*div<SVE_F:mode>3): Generalize to... (*<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this. Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org> From-SVN: r274419
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