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authorWilco Dijkstra <wdijkstr@arm.com>2016-02-10 12:52:23 +0000
committerWilco Dijkstra <wilco@gcc.gnu.org>2016-02-10 12:52:23 +0000
commit00a8574af2b7df89e82dab3c415de8b7cb48a333 (patch)
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Enable instruction fusion of dependent AESE; AESMC and AESD; AESIMC pairs.
This can give up to 2x speedup on many AArch64 implementations. Also model the crypto instructions on Cortex-A57 according to the Optimization Guide. gcc/ * config/aarch64/aarch64.c (cortexa53_tunings): Enable AES fusion. (cortexa57_tunings): Likewise. (cortexa72_tunings): Likewise. (arch_macro_fusion_pair_p): Add support for AES fusion. * config/aarch64/aarch64-fusion-pairs.def: Add AES_AESMC entry. * config/arm/aarch-common.c (aarch_crypto_can_dual_issue): Allow virtual registers before reload so early scheduling works. * config/arm/cortex-a57.md (cortex_a57_crypto_simple): Use correct latency and pipeline. (cortex_a57_crypto_complex): Likewise. (cortex_a57_crypto_xor): Likewise. (define_bypass): Add AES bypass. From-SVN: r233268
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