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| author | Umesh Kalappa <ukalappa.mips@gmail.com> | 2025-08-15 07:35:40 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-08-15 07:36:29 -0600 |
| commit | ef5f0e9c510231d56aebdaa1a3db9b41a962d23c (patch) | |
| tree | 3179e019c14c4073d0daea6d53e7e335e0f0da58 /libjava/java | |
| parent | 7232a131d7c672995989750e0f11020b0f5789d2 (diff) | |
| download | gcc-ef5f0e9c510231d56aebdaa1a3db9b41a962d23c.zip gcc-ef5f0e9c510231d56aebdaa1a3db9b41a962d23c.tar.gz gcc-ef5f0e9c510231d56aebdaa1a3db9b41a962d23c.tar.bz2 | |
RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.
Addressed the comments and tested "runtest --tool gcc --target_board='riscv-sim/-march=rv64gc_zba_zbb_zbc_zbs/-mabi=lp64/-mcmodel=medlow' riscv.exp" and 32 bit too
lint warnings can be ignored for riscv-ext.opt.
gcc/ChangeLog:
* config/riscv/riscv-ext-mips.def (DEFINE_RISCV_EXT):
Added mips prefetch extension.
* config/riscv/riscv-ext.opt: Generated file.
* config/riscv/riscv.md (prefetch):
Added mips prefetch address operand constraint.
* config/riscv/constraints.md: Added mips specific constraint.
* config/riscv/predicates.md (prefetch_operand):
Updated for mips nine bits offset.
* config/riscv/riscv.cc (riscv_prefetch_offset_address_p):
Legitimate address with offset for prefetch check.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.h:
Macros to support for mips cached type.
* doc/riscv-ext.texi: Updated for mips prefetch.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mipsprefetch.c: Test file for mips.pref.
Diffstat (limited to 'libjava/java')
0 files changed, 0 insertions, 0 deletions