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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-06-26 11:38:30 +0800
committerPan Li <pan2.li@intel.com>2023-06-26 19:04:37 +0800
commit9f76f04be40adffb2d3498010a23051502031140 (patch)
treeea59602338aafa26f4cd6b7cdd2dc9e477554cf5 /libjava/java
parentab6eac20f00761695c69b555f6b0a026bc25770d (diff)
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RISC-V: Remove redundant vcond patterns
Previously, Richi has suggested that vcond patterns are only needed when target support comparison + select consuming 1 instruction. Now, I do the experiments on removing those "vcond" patterns, it works perfectly. All testcases PASS. Really appreicate Richi helps us recognize such issue. Now remove all "vcond" patterns as Richi suggested. gcc/ChangeLog: * config/riscv/autovec.md (vcond<V:mode><VI:mode>): Remove redundant vcond patterns. (vcondu<V:mode><VI:mode>): Ditto. * config/riscv/riscv-protos.h (expand_vcond): Ditto. * config/riscv/riscv-v.cc (expand_vcond): Ditto.
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