RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

This patch will add testcase for unsigned integer SAT_ADD form 7:

  #define DEF_SAT_U_ADD_FMT_7(WT, T)     \
  T __attribute__((noinline))            \
  sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
  {                                      \
    T max = -1;                          \
    WT val = (WT)x + (WT)y;              \
    return val > max ? max : (T)val;     \
  }

  DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions