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authorEric Botcazou <ebotcazou@adacore.com>2012-02-13 21:51:44 +0000
committerEric Botcazou <ebotcazou@gcc.gnu.org>2012-02-13 21:51:44 +0000
commitf3f5e3c32e4c12719938848007dea246149b0255 (patch)
tree6cd5ac5a27e75203a69a3315e21aea845631ab15 /libitm/config/sparc/target.h
parent255a9a1bb5ed771c8b1f72ffb71bfdf77f2d9fb9 (diff)
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configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9. * config/sparc/cacheline.h: New file. * config/sparc/target.h: Likewise. * config/sparc/sjlj.S: Likewise. * config/linux/sparc/futex_bits.h: Likewise. From-SVN: r184177
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diff --git a/libitm/config/sparc/target.h b/libitm/config/sparc/target.h
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+/* Copyright (C) 2012 Free Software Foundation, Inc.
+
+ This file is part of the GNU Transactional Memory Library (libitm).
+
+ Libitm is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+namespace GTM HIDDEN {
+
+typedef struct gtm_jmpbuf
+{
+ void *cfa;
+ unsigned long pc;
+} gtm_jmpbuf;
+
+/* UltraSPARC processors generally use a fixed page size of 8K. */
+#define PAGE_SIZE 8192
+#define FIXED_PAGE_SIZE 1
+
+/* The size of one line in hardware caches (in bytes). We use the primary
+ cache line size documented for the UltraSPARC T1/T2. */
+#define HW_CACHELINE_SIZE 16
+
+static inline void
+cpu_relax (void)
+{
+ __asm volatile ("" : : : "memory");
+}
+
+} // namespace GTM