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| author | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-08-16 22:28:50 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-16 22:30:00 -0600 |
| commit | e7a36e4715c7162ccfd7cd32da985d629bbd9c61 (patch) | |
| tree | c58b0bff10ddce793312edd316bce8938001b3ef /libgomp | |
| parent | a32de58c9e6394e4e6aef0ac95b52d1c774ac8bc (diff) | |
| download | gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.zip gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.tar.gz gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.tar.bz2 | |
[PATCH] RISC-V: Support simplify (-1-x) for vector.
From: Yanzhang Wang <yanzhang.wang@intel.com>
The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2,e32,m1,ta,ma
vrsub.vi v1,v1,-1
vs1r.v v1,0(a0)
ret
to,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2,e32,m1,ta,ma
vnot.v v1,v1
vs1r.v v1,0(a0)
ret
gcc/ChangeLog:
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Use
CONSTM1_RTX.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/simplify-vrsub.c: New test.
Diffstat (limited to 'libgomp')
0 files changed, 0 insertions, 0 deletions