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| author | Lulu Cheng <chenglulu@loongson.cn> | 2023-12-01 11:51:51 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2023-12-08 15:38:53 +0800 |
| commit | f6cc6eb5b6c7833385f66dbc878e8f6ec1ebdb8f (patch) | |
| tree | 6fd27b4d55164453639db565196538ed786d2194 /libgomp/target.c | |
| parent | 2b2a0599e221786c2f019f1e8c02c80d23c71430 (diff) | |
| download | gcc-f6cc6eb5b6c7833385f66dbc878e8f6ec1ebdb8f.zip gcc-f6cc6eb5b6c7833385f66dbc878e8f6ec1ebdb8f.tar.gz gcc-f6cc6eb5b6c7833385f66dbc878e8f6ec1ebdb8f.tar.bz2 | |
LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.
The instructions defined in LoongArch Reference Manual v1.1 are not the instruction
set v1.1 version. The CPU defined later may only support some instructions in
LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and
related definitions are removed here.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro.
(fill_native_cpu_config): Define a new variable hw_isa_evolution record the
extended instruction set support read from cpucfg.
* config/loongarch/loongarch-def.cc: Set evolution at initialization.
* config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete.
(ISA_BASE_LA64V110): Likewise.
(N_ISA_BASE_TYPES): Likewise.
(defined): Likewise.
* config/loongarch/loongarch-opts.cc: Likewise.
* config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise.
(ISA_BASE_IS_LA64V110): Likewise.
* config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise.
* config/loongarch/loongarch.opt: Regenerate.
Diffstat (limited to 'libgomp/target.c')
0 files changed, 0 insertions, 0 deletions