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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-02-01 09:47:33 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-02-03 14:57:38 +0800 |
| commit | f3a10f4fff3d6751aa65df58b8629f84a0c04545 (patch) | |
| tree | debe353dea71c282a70b93f520713c1742995e1e /libgomp/target.c | |
| parent | d8bd2c5f22eaa96b703531c41f7c2e6685d43584 (diff) | |
| download | gcc-f3a10f4fff3d6751aa65df58b8629f84a0c04545.zip gcc-f3a10f4fff3d6751aa65df58b8629f84a0c04545.tar.gz gcc-f3a10f4fff3d6751aa65df58b8629f84a0c04545.tar.bz2 | |
RISC-V: Fix constraint bug for binary operation
Current constraint configuration will generate:
vadd.vv v0,v24,v25,v0.t
vsll.vx v0,v24,a5,v0.t
They are incorrect according to RVV ISA.
This patch fix this obvious issue.
gcc/ChangeLog:
* config/riscv/vector-iterators.md (sll.vi): Fix constraint bug.
(sll.vv): Ditto.
(%3,%4): Ditto.
(%3,%v4): Ditto.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vv_constraint-1.c:
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c:
Diffstat (limited to 'libgomp/target.c')
0 files changed, 0 insertions, 0 deletions