diff options
| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-06-06 23:35:52 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-06-16 13:52:23 +0100 |
| commit | d20b2ad845876eec0ee80a3933ad49f9f6c4ee30 (patch) | |
| tree | 184f2b31fba4f05d4c42515a84ddd847fd7a9cba /libgomp/target.c | |
| parent | ffb87344dd343df60eafb10d510ac704f37417ca (diff) | |
| download | gcc-d20b2ad845876eec0ee80a3933ad49f9f6c4ee30.zip gcc-d20b2ad845876eec0ee80a3933ad49f9f6c4ee30.tar.gz gcc-d20b2ad845876eec0ee80a3933ad49f9f6c4ee30.tar.bz2 | |
aarch64: [US]Q(R)SHR(U)N scalar forms refactoring
Some instructions from the previous patch have scalar forms:
SQSHRN,SQRSHRN,UQSHRN,UQRSHRN,SQSHRUN,SQRSHRUN.
This patch converts the patterns for these to use standard RTL codes.
Their MD patterns deviate slightly from the vector forms mostly due to
things like operands being scalar rather than vectors.
One nuance is in the SQSHRUN,SQRSHRUN patterns. These end in a truncate
to the scalar narrow mode e.g. SI -> QI. This gets simplified by the
RTL passes to a subreg rather than keeping it as a truncate.
So we end up representing these without the truncate and in the expander
read the narrow subreg in order to comply with the expected width of the
intrinsic.
Bootstrapped and tested on aarch64-none-linux-gnu and
aarch64_be-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>):
Rename to...
(aarch64_<shrn_op>shrn_n<mode>): ... This. Reimplement with RTL codes.
(*aarch64_<shrn_op>rshrn_n<mode>_insn): New define_insn.
(aarch64_sqrshrun_n<mode>_insn): Likewise.
(aarch64_sqshrun_n<mode>_insn): Likewise.
(aarch64_<shrn_op>rshrn_n<mode>): New define_expand.
(aarch64_sqshrun_n<mode>): Likewise.
(aarch64_sqrshrun_n<mode>): Likewise.
* config/aarch64/iterators.md (V2XWIDE): Add HI and SI modes.
Diffstat (limited to 'libgomp/target.c')
0 files changed, 0 insertions, 0 deletions