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| author | Thomas Schwinge <thomas@codesourcery.com> | 2023-11-16 23:17:36 +0100 |
|---|---|---|
| committer | Thomas Schwinge <thomas@codesourcery.com> | 2023-11-30 15:42:57 +0100 |
| commit | 9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0 (patch) | |
| tree | 279ac00a8da15901d41b0600a74b45aede3bd1f3 /libgomp/omp_lib.f90.in | |
| parent | 318f5232cfb3e0c9694889565e1f5424d0354463 (diff) | |
| download | gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.zip gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.tar.gz gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.tar.bz2 | |
GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases
... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers". This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.
gcc/testsuite/
* gcc.target/gcn/avgpr-mem-double.c: Remove
'dg-skip-if "incompatible ISA" [...]'.
* gcc.target/gcn/avgpr-mem-int.c: Likewise.
* gcc.target/gcn/avgpr-mem-long.c: Likewise.
* gcc.target/gcn/avgpr-mem-short.c: Likewise.
* gcc.target/gcn/avgpr-spill-double.c: Likewise.
* gcc.target/gcn/avgpr-spill-int.c: Likewise.
* gcc.target/gcn/avgpr-spill-long.c: Likewise.
* gcc.target/gcn/avgpr-spill-short.c: Likewise.
Diffstat (limited to 'libgomp/omp_lib.f90.in')
0 files changed, 0 insertions, 0 deletions