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| author | Pan Li <pan2.li@intel.com> | 2023-08-17 10:04:51 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-17 15:34:53 +0800 |
| commit | 20e1db413ee8bb4d5233d97484e19e4e1d85f4ac (patch) | |
| tree | bba5cd746b4a90a41992ebd4cd1effc714e06cee /libgomp/allocator.c | |
| parent | 72fc7e9d6aefbc4de1d3827062e47277fca83ef5 (diff) | |
| download | gcc-20e1db413ee8bb4d5233d97484e19e4e1d85f4ac.zip gcc-20e1db413ee8bb4d5233d97484e19e4e1d85f4ac.tar.gz gcc-20e1db413ee8bb4d5233d97484e19e4e1d85f4ac.tar.bz2 | |
RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFNCVT.F.{X|XU|F}.W as the below samples.
* __riscv_vfncvt_f_x_w_f32m1_rm
* __riscv_vfncvt_f_x_w_f32m1_rm_m
* __riscv_vfncvt_f_xu_w_f32m1_rm
* __riscv_vfncvt_f_xu_w_f32m1_rm_m
* __riscv_vfncvt_f_f_w_f32m1_rm
* __riscv_vfncvt_f_f_w_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfncvt_f): Add frm_op_type template arg.
(vfncvt_f_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_f_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test.
Diffstat (limited to 'libgomp/allocator.c')
0 files changed, 0 insertions, 0 deletions