This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.

When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.

2016-02-02  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
	* config/aarch64/aarch64.c
	(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
	(aarch64_ira_change_pseudo_allocno_class): New function.

    gcc/testsuite/
	* gcc.target/aarch64/scalar_shift_1.c
	(test_corners_sisd_di): Improve force to SIMD register.
	(test_corners_sisd_si): Likewise.
	* gcc.target/aarch64/vect-ld1r-compile-fp.c:
	Remove scan-assembler check for ldr.

From-SVN: r233083

0 files changed, 0 insertions, 0 deletions