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| author | Mihail Ionescu <mihail.ionescu@arm.com> | 2020-01-17 17:56:41 +0000 |
|---|---|---|
| committer | Mihail Ionescu <mihail.ionescu@arm.com> | 2020-01-17 18:50:38 +0000 |
| commit | 60d616b1f6deffcc57a4114f1a31559a17a3923c (patch) | |
| tree | 2249d70f1506a4236544f25cb590578bfb3fceec /libgfortran/io/unit.c | |
| parent | 674dcc3f738c4be2bc7d51d72d98fb1c0d2ebea2 (diff) | |
| download | gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.zip gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.tar.gz gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.tar.bz2 | |
[GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline
This patch is adding the following instructions:
ASRL (reg)
LSLL (reg)
*** gcc/ChangeLog ***
2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Sudakshina Das <sudi.das@arm.com>
* config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
(ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
* config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
register pairs for doubleword quantities for ARMv8.1M-Mainline.
* config/arm/thumb2.md (thumb2_asrl): New.
(thumb2_lsll): Likewise.
2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Sudakshina Das <sudi.das@arm.com>
* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.
Diffstat (limited to 'libgfortran/io/unit.c')
0 files changed, 0 insertions, 0 deletions