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author | Christophe Lyon <christophe.lyon@st.com> | 2019-09-20 15:32:20 +0200 |
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committer | Christophe Lyon <clyon@gcc.gnu.org> | 2019-09-20 15:32:20 +0200 |
commit | 76c93295f3b3fec8f34fccbb2c5d574c1362752a (patch) | |
tree | 004428d1e92c6e1eaa3a4b75e257d12249a40021 /libgcc | |
parent | 264c073993e2887308144fc8e27e2bf4a3bcd353 (diff) | |
download | gcc-76c93295f3b3fec8f34fccbb2c5d574c1362752a.zip gcc-76c93295f3b3fec8f34fccbb2c5d574c1362752a.tar.gz gcc-76c93295f3b3fec8f34fccbb2c5d574c1362752a.tar.bz2 |
Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture
This is causing regressions when mixing with user code compiled in ARM mode.
2019-09-20 Christophe Lyon <christophe.lyon@st.com>
Revert:
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
architecture.
From-SVN: r276001
Diffstat (limited to 'libgcc')
-rw-r--r-- | libgcc/ChangeLog | 9 | ||||
-rw-r--r-- | libgcc/config/arm/unwind-arm.c | 5 |
2 files changed, 9 insertions, 5 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 37fadd4..74deb0f 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,12 @@ +2019-09-20 Christophe Lyon <christophe.lyon@st.com> + + Revert: + 2019-09-10 Christophe Lyon <christophe.lyon@st.com> + Mickaël Guêné <mickael.guene@st.com> + + * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only + architecture. + 2019-09-19 Richard Henderson <richard.henderson@linaro.org> * config/aarch64/lse-init.c: New file. diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 8313ee0..9ba73e7 100644 --- a/libgcc/config/arm/unwind-arm.c +++ b/libgcc/config/arm/unwind-arm.c @@ -199,11 +199,6 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context, return _UVRSR_FAILED; vrs->core.r[regno] = *(_uw *) valuep; -#if defined(__thumb__) - /* Force LSB bit since we always run thumb code. */ - if (regno == R_PC) - vrs->core.r[regno] |= 1; -#endif return _UVRSR_OK; case _UVRSC_VFP: |